Datasheet

15
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
WUU U
Figure 8. LTC1149 Series Layout Diagram (see Layout Checklist)
in series with each sense lead to help decouple Pins 8
and 9. However, when these resistors are used, the
capacitor should be no larger than 1000pF.
4. Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? An addi-
tional 0.1µF ceramic capacitor between V
IN
and power
ground may be required in some applications.
5. Is the V
CC
decoupling capacitor connected closely
between Pin 5 of the LTC1149 and power ground? This
capacitor carries the MOSFET driver peak currents.
6. Is the SHDN1 Pin 10 (fixed output versions only)
actively pulled to ground during normal operation? The
SHDN1 pin is high impedance and must not be allowed
to float. In adjustable versions, Pin 10 is the feedback
pin and is very sensitive to pickup from the switch node.
Care must be taken to isolate V
FB
from possible capaci-
tive coupling of the inductor switch signal.
Troubleshooting Hints
Since efficiency is critical to LTC1149 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 6.
In continuous mode (I
LOAD
> I
BURST
) the voltage on Pin 6
should be a sawtooth with a 0.9V
P-P
swing. This voltage
should never dip below 2V as shown in Figure 9a.
When load currents are low (I
LOAD
< I
BURST
) Burst Mode
operation should occur with the C
T
pin waveform periodi-
cally falling to ground as shown in Figure 9b.
If Pin 6 is observed falling to ground at high output
currents, it indicates poor decoupling or improper ground-
ing. Refer to the Board Layout Checklist.
Figure 9. C
T
Pin 6 Waveforms
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION
1149 F09
1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

PGATE
V
IN

V
CC

PDRIVE
V
CC

C
T

I
TH

SENSE
–
CAP
SD2
RGND
NGATE
PGND
SGND
C
OUT
D1
P-CHANNEL
1k
3300pFC
T
R1
R2
R
SENSE
N-CHANNEL
C
IN
L
+
–
–
+
V
OUT
V
IN
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
BOLD LINES INDICATE HIGH CURRENT PATHS
1149 F08
1000pF
V
FB
/ 
SHDN1
SENSE
+
100pF
+
1µF
0.068µF
1N4148
1N4148
SHUTDOWN
0.047µF
+
+