Datasheet

15
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1148 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 9. Check the following
in your layout:
1. Are the signal and power grounds segregated? The
LTC1148 signal ground Pin 11 must return to the (–)
plate of C
OUT
. The power ground returns to the
source of the N-channel MOSFET, anode of the
Schottky diode, and (–) plate of C
IN
, which should
have as short lead lengths as possible.
2. Does the LTC1148 SENSE
–
Pin 7 connect to a point
close to R
SENSE
and the (+) plate of C
OUT
? In adjust-
able applications, the resistive divider R1, R2 must be
connected between the (+) plate of C
OUT
and signal
ground.
3. Are the SENSE
–
and SENSE
+
leads routed together
with minimum PC trace spacing? The 1000pF capacitor
between Pins 7 and 8 should be as close as possible to
the LTC1148.
4. Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? This capaci-
tor provides the AC current to the P-channel MOSFET.
5. Is the 1µF V
IN
decoupling capacitor connected closely
between Pin 3 and power ground Pin 12? This capacitor
carries the MOSFET driver peak currents.
6. Is the Shutdown Pin 10 actively pulled to ground during
normal operation? The Shutdown pin is high imped-
ance and must not be allowed to float.
Figure 9. LTC1148 Layout Diagram (See Board Layout Checklist)
APPLICATIO S I FOR ATIO
WUU U
1
2
3
4
5
6
7
14
13
12
11
10
9
8
C
OUT
1µF
D1
P-CHANNEL
1k
3300pF10nFC
T
LTC1148
R1
R2
+
R
SENSE
N-CHANNEL
+
C
IN
L
+
–
–
+
V
OUT
V
IN
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
BOLD LINES INDICATE HIGH CURRENT PATHS
LTC1148 • F09
SHUTDOWN
1000pF
P-DRIVE
V
IN
C
T
INTV
CC
I
TH
SENSE
–
N-DRIVE
PGND
SGND
SHDN
NC (V
FB
)
SENSE
+
NC NC
+