Datasheet

14
LTC1148
LTC1148-3.3/LTC1148-5
114835fd
APPLICATIO S I FOR ATIO
WUU U
With the addition of R3, a current is generated through R1
causing an offset of:
V
OFFSET
= V
OUT
) )
R1
R1 + R3
If V
OFFSET
> 25mV, the minimum threshold will be can-
celled and Burst Mode operation is prevented from occur-
ring. Since V
OFFSET
is constant, the maximum load current
is also decreased by the same offset. Thus, to get back to
the same I
MAX
, the value of the sense resistor must be
lower:
R
SENSE
≈
75mV
I
MAX
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 7 and 8.
Output Crowbar
An added feature to using an N-channel MOSFET as the
synchronous switch is the ability to crowbar the output
with the same MOSFET. Pulling the timing capacitor Pin
4 above 1.5V when the output voltage is greater than the
desired regulated value will turn “on” the N-channel
MOSFET.
A fault condition which causes the output voltage to go
above a maximum allowable value can be detected by
external circuitry. Turning on the N-channel MOSFET
when this fault is detected will cause large currents to flow
and blow the system fuse.
The N-channel MOSFET needs to be sized so it will safely
handle this overcurrent condition. The typical delay from
pulling the C
T
pin high and the N drive Pin 14 going high
is 250ns. Note: Under shutdown conditions, the N-chan-
nel is held OFF and pulling the C
T
pin high will not cause
the N-channel MOSFET to crowbar the output.
A simple N-channel FET can be used as an interface
between the overvoltage detect circuitry and the LTC1148
as shown in Figure 7.
Figure 7. Output Crowbar Interface
LTC1148
INTV
CC
C
T
VN2222LL
5
4
FROM CROWBAR DETECT CIRCUIT
(ACTIVE WHEN V
GATE
= V
IN
OFF WHEN V
GATE
= GROUND)
LTC1148 • F07
Troubleshooting Hints
Since efficiency is critical to LTC1148 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 4.
In continuous mode (I
LOAD
> I
BURST
) the voltage on the C
T
pin should be a sawtooth with a 0.9V
P-P
swing. This
voltage should never dip below 2V as shown in Figure 8a.
When load currents are low (I
LOAD
< I
BURST
) Burst Mode
operation should occur with the C
T
pin waveform periodi-
cally falling to ground as shown in Figure 8b.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION
LTC1148 • F08
Figure 8. C
T
Waveforms
If Pin 4 is observed falling to ground at high output
currents, it indicates poor decoupling or improper ground-
ing. Refer to the Board Layout Checklist.