Datasheet

LTC1096/LTC1096L
LTC1098/LTC1098L
27
10968fc
TYPICAL APPLICATIONS
Interfacing to the Parallel Port of the
Intel 8051 Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1098(L) and parallel port mi-
croprocessors. Normally the CS, CLK and D
IN
signals
would be generated on three port lines and the D
OUT
signal
read on a fourth port line. This works very well. However,
we will demonstrate here an interface with the D
IN
and
D
OUT
of the LTC1098(L) tied together as described in the
SERIAL INTERFACE section. This saves one wire.
The 8051 fi rst sends the start bit and MUX address to the
LTC1098(L) over the data line connected to P1.2. Then
P1.2 is reconfi gured as an input (by writing to it a one) and
the 8051 reads back the 8-bit A/D result over the same
data line.
D
OUT
from LTC1098(L) Stored in 8051 RAM
CS
CLK
D
OUT
D
IN
LTC1098(L)
ANALOG
INPUTS
P1.4
P1.3
P1.2
8051
MUX ADDRESS
A/D RESULT
10968 TA06
R2
10968 TA07
MSB
LSB
B7 B6 B5 B4 B3 B2 B1 B0
1
CS
CLK
DATA (D
IN
/D
OUT
)
START
ODD/
SIGN
MSBF
B7
MSBF BIT LATCHED
BY LTC1098(L)
LTC1098(L) SENDS A/D RESULT
BACK TO 8051 P1.2
8051 P1.2 OUTPUTS DATA
TO LTC1098(L)
8051 P1.2 RECONFIGURED
AS AN INPUT AFTER THE 4TH RISING
CLK AND BEFORE THE 4TH FALLING CLK
LTC1098(L) TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
234
SGL/
DIFF
B6 B5 B4 B3 B2 B1 B0
10968 TA08
LABEL MNEMONIC OPERAND COMMENTS
LOOP 1
LOOP
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
SETB
A, #FFH
P1.4
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #09
C, P1.2
A
P1.3
P1.3
R4, LOOP
R2, A
P1.4
D
IN
word for LTC1098(L)
Make sure CS is high
CS goes low
Load counter
Rotate D
IN
bit into Carry
CLK goes low
Output D
IN
bit to LTC1098(L)
CLK goes high
Next bit
Bit 2 becomes an input
CLK goes low
Load counter
Read data bit into Carry
Rotate data bit into Acc.
CLK goes high
CLK goes low
Next bit
Store MSBs in R2
CS goes high