Datasheet

LTC1063
8
1063fa
V
–
50k
V
+
0.1µF
V
OUT
1063 TC01
0.1µF
CLOCK IN
–
+
LT1022
20pF
V
IN
50k
8
7
6
5
1
2
3
4
LTC1063
CLOCK FREQUENCY (MHz)
1
MAXIMUM LOAD CAPACITANCE (pF )
200
180
160
140
120
100
80
60
40
20
0
310
1063 F02
245
6
78
9
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±7.5V
T
A
= 25°C
Output Pin (Pin 7, N Package)
Pin 7 is the filter output. This pin can typically source over
20mA and sink 2mA. Pin 7 should not drive long coax
cables, otherwise the filter’s total harmonic distortion will
degrade.
Clock Input Pin (Pin 5, N Package)
An external clock when applied to pin 5 tunes the filter
cutoff frequency. The clock-to-cutoff frequency ratio is
100:1. The high (V
HIGH
) and low (V
LOW
) clock logic
threshold levels are illustrated in Table 2. Square wave
clocks with duty cycles between 30% and 50% are strongly
recommended. Sinewave clocks are not recommended.
Clock Output Pin (Pin 4, N Package)
Any external clock applied to the clock input pin appears
at the clock output pin. The duty cycle of the clock output
equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
supply rails. When the LTC1063 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
clock output pin with a 30% duty cycle. The clock output
pin can be used to drive other LTC1063s or other ICs. The
maximum capacitance, C
L(MAX)
, the clock output pin can
drive is illustrated in Figure 2.
Table 2. Clock Pin Threshold Levels
POWER SUPPLY V
HIGH
V
LOW
V
S
= ±2.5V 1.5V 0.5V
V
S
= ±5V 3V 1V
V
S
= ±7.5V 4.5V 1.5V
V
S
= ±8V 4.8V 1.6V
V
S
= 5V, 0V 4V 3V
V
S
= 12, 0V 9.6V 7.2V
V
S
=15V, 0V 12V 9V
Figure 3. Test Circuit for THD
Figure 2. Maximum Load Capacitance at the Clock Output Pin
TEST CIRCUIT
PI FU CTIO S
UUU