Datasheet

5
LTC1062
1062fd
8
7
6
5
1
2
3
4
SWITCHED
CAPACITOR
NETWORK
CLOCK GEN
÷ 1, 2, 4 OSC
B
OUT
OUT
V
+
C
OSC
1062 BD
÷
V
AGND
FB
f
CLK
×1
BY CONNECTING PIN 4 TO V
+
, AGND OR V
, THE
OUTPUT FREQUENCY OF THE INTERNAL CLOCK
GENERATOR IS THE OSCILLATOR FREQUENCY DI-
VIDED BY 1, 2, 4. THE (f
CLK
/f
C
) RATIO OF 100:1 IS
WITH RESPECT TO THE INTERNAL CLOCK GENERA-
TOR OUTPUT FREQUENCY. PIN 5 CAN BE DRIVEN
WITH AN EXTERNAL CMOS LEVEL CLOCK. THE
LTC1062 CAN ALSO BE SELF-CLOCKED BY CON-
NECTING AN EXTERNAL CAPACITOR (C
OSC
) TO
GROUND (OR TO V
IF C
OSC
IS POLARIZED). UNDER
THIS CONDITION AND WITH ±5V SUPPLIES, THE
INTERNAL OSCILLATOR FREQUENCY IS:
f
OSC
140kHz [33pF/(33pF + C
OSC
)]
AC TEST CIRCUIT
FB
AGND
V
DIVIDER
RATIO
B
OUT
OUT
V
+
C
OSC
1
2
3
4
8
7
6
5
LTC1062
0.1µF
MEASURED
OUTPUT
7
4
8
1
6
0.1µF
1062 F01
C = 0.01µF
V
IN
R = 25.8k
50
5V
–5V
2
3
–5V
5V
f
CLK
= 100kHz
5V
V
= –5V
R
+
LTC1052
1
2πRC
FOR BEST MAX FLAT APPROXIMATION,
THE INPUT RC SHOULD BE SUCH AS:
A 0.5k RESISTOR, R, SHOULD BE USED IF
THE BIPOLAR EXTERNAL CLOCK IS APPLIED
BEFORE THE POWER SUPPLIES TURN ON
1
1.63
f
CLK
100
=
For Adjusting Oscillator Frequency, Insert a 50k Pot in Series with C
OSC
. Use Two Times Calculated C
OSC
Figure 1
BLOCK DIAGRA
W