Datasheet

LTC1052/LTC7652
6
1052fa
50µV
10µV
5µV
Response Time vs Overdrive
V
REF
+ OVERDRIVE
20ms/DIV
TYPICAL PERFOR A CE CHARACTERISTICS
UW
OUTPUT
–5V
5V
V
REF
– 1mV
INPUT
{
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Electrical Characteristics Test Circuit (TC1) DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3)
THEORY OF OPERATIO
U
DC OPERATION
The shaded portion of the LTC1052 block diagram
(Figure 1a) entirely determines the amplifier’s DC
characteristics. During the auto zero portion of the cycle,
the g
m1
inputs are shorted together and a feedback path is
closed around the input stage to null its offset. Switch S2
and capacitor C
EXTA
act as a sample-and-hold to store the
nulling voltage during the next step—the sampling cycle.
In the sampling cycle, the zeroed amplifier is used to
amplify the differential input voltage. Switch S2 connects
the amplified input voltage to C
EXTB
and the output gain
stage. C
EXTB
and S2 act as a sample-and-hold to store the
amplified input signal during the auto zero cycle.
By switching between these two states at a frequency
much higher than the signal frequency, a continuous
output results.
Notice that during the auto zero cycle the g
m1
inputs are
not only shorted together, but are also shorted to the
inverting input. This forces nulling with the common mode
voltage present and accounts for the extremely high
CMRR of the LTC1052. In the same fashion, variations in
0.1µF
0.1µF
R1
1k
R2
1M
3
2
7
6
8
4
1
V
–
V
+
+
–
LTC1052
LTC1052/7652 • TC01
OUTPUT
R
L
TEST CIRCUITS
0.1µF
0.1µF
6
R2
3
2
7
6
8
4
1
V
–
V
+
+
–
LTC1052
LTC1052/7652 • TC02
OUTPUT
(NOISE x 20,000)
34k
R1
C2
3
2
+
–
LT1001
34k
C3
R4
R3
BANDWIDTH
10Hz
1Hz
R1
16.2Ω
16.2Ω
R2
162k
162k
R3
16.2k
162k
R4
16.2k
162k
C2
0.1µF
1.0µF
C3
1.0µF
1.0µF
C4
1.0µF
1.0µF
C4