Datasheet
3
LTC1046
1046fb
OSCILLATOR FREQUENCY, f
OSC
(Hz)
100
80
POWER CONVERSION EFFICIENCY, P
EFF
(%)
86
92
98
100
1k 10k 100k 1M
1046 G06
96
94
90
88
84
82
V
+
= 5V
T
A
= 25°C
C1 = C2
A = 100µF, 1mA
B = 100µF, 15mA
C = 10µF, 1mA
D = 10µF, 15mA
E = 1µF, 1mA
F = 1µF, 15mA
A
C
B
E
D
F
LOAD CURRENT, I
L
(mA)
0
30
POWER CONVERSION EFFICIENCY, P
EFF
(%)
50
60
70
80
90
100
30 40 60 70
1046 G05
40
10 20 50
P
EFF
I
S
20
10
0
T
A
= 25°C
V
+
= 5V
C1 = C2 = 10µF
f
OSC
= 30kHz
30
50
60
70
80
90
100
40
20
10
0
SUPPLY CURRENT (mA)
LOAD CURRENT, I
L
(mA)
0
30
POWER CONVERSION EFFICIENCY, P
EFF
(%)
50
60
70
80
90
100
34 67
1046 G04
40
12 5
P
EFF
I
S
20
10
0
T
A
= 25°C
V
+
= 2V
C1 = C2 = 10µF
f
OSC
= 8kHz
8910
3
5
6
7
8
9
10
4
2
1
0
SUPPLY CURRENT (mA)
AMBIENT TEMPERATURE (°C)
–55
10
OUTPUT RESISTANCE (Ω)
30
40
50
60
70
80
25 50 100 125
1046 G03
20
–25 0 75
C1 = C2 = 10µF
V
+
= 2V, C
OSC
= 0pF
V
+
= 5V, C
OSC
= 0pF
OSCILLATOR FREQUENCY, f
OSC
(Hz)
100
0
OUTPUT RESISTANCE, R
O
(Ω)
200
300
400
500
1k 10k 100k
1046 G01
100
T
A
= 25°C
V
+
= 5V
I
L
= 10mA
C1 = C2
= 1µF
C1 = C2
= 10µF
C1 = C2
= 100µF
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
(Using Test Circuit in Figure 1)
Output Resistance vs Output Resistance vs Output Resistance vs
Oscillator Frequency Supply Voltage Temperature
Power Conversion Efficiency vs Power Conversion Efficiency vs Power Conversion Efficiency vs
Load Current for V
+
= 2V Load Current for V
+
= 5V Oscillator Frequency
SUPPLY VOLTAGE, V
+
(V)
0
10
OUTPUT RESISTANCE, R
O
(Ω)
100
1000
2567
1046 G02
134
T
A
= 25°C
I
L
= 3mA
C
OSC
= 100pF
C
OSC
= 0pF
Note 1: Absolute Maximum Ratings are those values beyond which
the life of the device may be impaired.
Note 2: Connecting any input terminal to voltages greater than V
+
or
less than ground may cause destructive latch-up. It is recommended
that no inputs from sources operating from external supplies be
applied prior to power-up of the LTC1046.
Note 3: R
OUT
is measured at T
J
= 25°C immediately after power-on.
Note 4: f
OSC
is tested with C
OSC
= 100pF to minimize the effects of test
fixture capacitance loading. The 0pF frequency is correlated to this 100pF
test point, and is intended to simulate the capacitance at pin 7 when the
device is plugged into a test socket and no external capacitor is used.
E
LECTR
IC
AL C CHARA TERIST
ICS