Datasheet

LTC1041
4
1041fa
APPLICATIO S I FOR ATIO
WUUU
The LTC1041 uses sampled data techniques to achieve
its unique characteristics. It consists of two comparators,
each of which has two differential inputs (Figure 1a).
When the sum of the voltages on a comparator’s inputs is
positive, the output is high and when the sum is negative,
the output is low. The inputs are interconnected such that
the R
S
flip-flop is reset (ON/OFF = GND) when
V
IN
> (SET POINT + DELTA) and is set (ON/OFF = V
+
) when
V
IN
< (SET POINT – DELTA). This makes a very precise
hysteresis loop of 2 • DELTA centered around the
SET POINT. (See Figure 1b.)
For R
S
< 10kΩ
The dual differential input structure is made with CMOS
switches and a precision capacitor array. Input
impedance characteristics of the LTC1041 can be
determined from the equivalent circuit shown in Figure 2.
The input capacitance will charge with a time constant of
V
P-P
Output Voltage
vs Load Current
R
IN
vs Sampling Frequency
LOAD CURRENT, I
L
(mA)
0
TYPICAL OUTPUT VOLTAGE DROP (V
+
– V
P-P
)
(V)
0.8
0.4
0
8
LTC1041 • TPC06
1.2
1.6
2.0
0.6
0.2
1.0
1.4
1.8
21
43
67 9
5
10
V
+
= 2.8V
V
+
= 16V
V
+
= 5V
V
+
= 10V
SAMPLING FREQUENCY f
S
(Hz)
1
10
7
AVERAGE INPUT RESISTANCE, R
IN
(1/f
S
• 66pF) (Ω)
10
9
10
11
10
2
10
4
10
3
10
LTC1041 • TPC07
10
8
10
10
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC1041 • AI01a
OSC
(6)
GND
(4)
DELTA
(5)
SET POINT
(3)
V
IN
(2)
C
EXT
R
EXT
POWER ON
V
P-P
(7)
V
+
(8)
ON/OFF
(1)
V
+
V
+
80µs
4
–
–
+
+
COMP B
4
TIMING
GENERATOR
V
P-P
CIRCUIT
–
–
+
+
COMP A
(a)
LTC1041 • AI01b
V
+
GND
0V
INPUT VOLTAGE, V
IN
V
L
V
U
SET POINT
DEADBAND
DELTA –
+
DELTA
ON/OFF OUTPUT
Figure 1. LTC1041 Block Diagram
(b)