Datasheet

LT8705
35
8705fb
For more information www.linear.com/LT8705
applicaTions inForMaTion
3. INT V
CC
current. This is the sum of the MOSFET driver
current, LDO33 pin current and control currents. The
INTV
CC
regulator’s input voltage times the current
represents lost power. This loss can be reduced by
supplying INTV
CC
current through the EXTV
CC
pin from
a high efficiency source, such as the output or alternate
supply if available. Also, lower capacitance MOSFETs
can reduce INTV
CC
current and power loss.
4. C
IN
and C
OUT
loss. The input capacitor has the difficult
job of filtering the large RMS input current to the regu-
lator in buck mode. The output capacitor has the more
d
i
fficult job of filtering the large RMS output current in
boost mode. Both C
IN
and C
OUT
are required to have
low ESR to minimize the AC I
2
R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
5. Other losses. Schottky diodes D1 and D2 are respon
-
sible for conduction losses during dead time and light
lo
ad conduction periods. Inductor core loss occurs
predominately at light loads.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If
one makes a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Circuit Board Layout Checklist
The basic circuit board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
• The ground plane layer should not have any traces and
should be as close as possible to the layer with the
power MOSFETs.
• The high di/dt path formed by switch M1, switch M2,
D1, R
SENSE
and the C
IN
capacitor should be compact
with short leads and PC trace lengths. The high di/dt
path formed by switch M3, switch M4, D2 and the C
OUT
capacitor also should be compact with short leads and
PC trace lengths. Two layout examples are shown in
Figures 13a and 13b.
GND
V
OUT
C
OUT
L
R
SENSE
8705 F13b
M4
M3M2
M1
SW1 SW2
D1
D2
V
IN
C
IN
LT8705
CKT
Figure 13. Switches Layout
(13a)
(13b)
M3 M4
M1 M2
LT8705
CKT
D2D1
V
OUT
V
IN
SW1 SW2
L
R
SENSE
GND
8705 F13a
C
OUT
C
IN
• Avoid running signal traces parallel to the traces that
carry high di/dt current because they can receive in-
ductively coupled voltage noise. This includes the SW1,
S
W
2, TG1 and TG2 traces to the controller.
• Use immediate vias to connect the components (includ
-
ing the LT8705’s GND pins) to the ground plane. Use
several vias for each power component.
• Minimize parasitic SW pin capacitance by removing
GND and V
IN
copper from underneath the SW1 and
SW2 regions.