Datasheet

LT8705
33
8705fb
For more information www.linear.com/LT8705
applicaTions inForMaTion
Loop Compensation
The loop stability is affected by a number of factors includ-
ing the inductor value, output capacitance, load current,
V
IN
, V
OUT
and the V
C
resistor and capacitors. The LT8705
uses internal transconductance error amplifiers driving V
C
to help compensate the control loop. For most applications
a 3.3nF series capacitor at V
C
is a good value. The parallel
capacitor (from V
C
to GND) is typically 1/10th the value
of the series capacitor to filter high frequency noise. A
larger V
C
series capacitor value may be necessary if the
output capacitance is reduced. A good starting value for
the V
C
series resistor is 20k. Lower resistance will improve
stability but will slow the loop response. Use a trim pot
instead of a fixed resistor for initial bench evaluation to
determine the optimum value.
LDO33 Pin Regulator
The LT8705 includes a low dropout regulator (LDO) to
regulate the LDO33 pin to 3.3V. This pin can be used to
power external circuitry such as a microcontroller or other
desired peripherals. The input supply for the LDO33 pin
regulator is INTV
CC
. Therefore INTV
CC
must have sufficient
voltage, typically >4.0V, to properly regulate LDO33. The
LDO33 and INTV
CC
regulators are enabled by the SHDN pin
and are not affected by SWEN. The LDO33 pin regulator
has overcurrent protection circuitry that typically limits
the output current to 17.25mA. An undervoltage lockout
monitoring LDO disables switching activity when LDO33
falls below 3.04V (typical). LDO33 should be bypassed
locally with 0.1µF or more.
Voltage Lockouts
The LT8705 contains several voltage detectors to make
sure the chip is under proper operating conditions. Table1
summarizes the pins that are monitored and also indicates
the state that the LT8705 will enter if an under or overvolt
-
age condition is detected.
The conditions are listed in order of priority from top
to bottom. If multiple over/undervoltage conditions are
detected, the chip will enter the state listed highest on
the table.
Due to their accurate thresholds, configurable undervolt
-
age lockouts (UVLOs) can be implemented using the
SHD
N, SWEN and in some cases, FBIN pin. The UVLO
function sets the turn on/off of the LT8705 at a desired
minimum input voltage. For example, a resistor divider
can be connected between V
IN
, SHDN and GND as shown
in Figures1 and 14. From the Electrical Characteristics,
SHDN has typical rising and falling thresholds of 1.234V
and 1.184V respectively. The falling threshold for turning
off switching activity can be chosen using:
R
SHDN1
=
R
SHDN2
• V
(IN,CHIP_OFF,FALLING)
–1.184V
(
)
1.184V
Ω
For example, choosing R
SHDN2
= 20k and a falling V
IN
threshold of 5.42V results in:
R
SHDN1
=
20kΩ• 5.42V –1.184V
(
)
1.184V
=71.5kΩ
The rising threshold for enabling switching activity would
be:
V
(IN,CHIP_OFF,RISING)
= V
(IN,CHIP_OFF,FALLING)
•
1.234V
1.184V
or 5.65V in this example.
Table 1: Voltage Lockout Conditions
PIN
APPROXIMATE
VOLTAGE
CONDITION
CHIP STATE
(FIGURE 2) READ SECTION
V
IN
<2.5V Chip Off Operation: Start-Up
SHDN <1.18V Chip Off
INTV
CC
and
GATEV
CC
<4.65V Switcher
Off
SWEN <1.18V Switcher
Off
LDO33 <3.04 Switcher
Off
IMON_IN >1.61V Fault Operation: Fault Conditions
IMON_OUT >1.61V Fault
FBIN <1.205V — Applications Information:
Input Voltage Regulation or
Undervoltage Lockout