Datasheet

LT8705
28
8705fb
For more information www.linear.com/LT8705
applicaTions inForMaTion
The maximum input ripple due to the voltage drop across
the ESR is approximately:
∆V
(BUCK,ESR)
≅
V
IN(MAX)
•I
OUT(MAX)
V
OUT(MIN)
•ESR
Output Capacitance: The output capacitance (C
OUT
) is
necessary to reduce the output voltage ripple caused by
discontinuities and ripple in the output and load currents.
The effects of ESR and the bulk capacitance must be
considered when choosing the right capacitor for a given
output ripple voltage. The steady-state output ripple due
to charging and discharging the bulk output capacitance
is given by the following equations:
∆V
BOOST,CAP
(
)
≅
I
OUT
•
V
OUT
–
V
IN
(
)
C
OUT
• V
IN
•f
V for V
OUT
> V
IN
∆V
(BUCK,CAP)
≅
V
OUT
• 1–
V
OUT
V
IN




8•L • f
2
•C
OU
T
V for V
OUT
< V
IN
The maximum output ripple due to the voltage drop across
the ESR is approximately:
∆V
(BOOST,ESR)
≅
V
OUT(MAX)
•I
OUT(MAX)
V
IN(MIN)
•ESR
As with C
IN
, multiple capacitors placed in parallel may
be needed to meet the ESR and RMS current handling
requirements.
Schottky Diode (D1, D2) Selection
The Schottky diodes, D1 and D2, shown in Figure 1, con
-
duct during the dead time between the conduction of the
p
o
wer MOSFET switches. They are intended to prevent
the body diodes of synchronous switches M2 and M4
from turning on and storing charge. For example, D2
significantly reduces reverse-recovery current between
switch M4 turn-off and switch M3 turn-on, which improves
converter efficiency, reduces switch M3 power dissipation
and reduces noise in the inductor current sense resistor
(R
SENSE
) when M3 turns on. In order for the diode to be
effective, the inductance between it and the synchronous
switch must be as small as possible, mandating that these
components be placed adjacently.
For applications with high input or output voltages (typi-
cally >40V) avoid Schottky diodes with excessive reverse-
le
akage currents particularly at high temperatures. Some
ultralow V
F
diodes will trade off increased high temperature
leakage current for reduced forward voltage. Diode D1
can have a reverse voltage up to V
IN
and D2 can have
a reverse voltage up to V
OUT
. The combination of high
reverse voltage and current can lead to self heating of
the diode. Besides reducing efficiency, this can increase
leakage current which increases temperatures even further.
Choose packages with lower thermal resistance (θ
JA
) to
minimize self heating of the diodes.
Topside MOSFET Driver Supply (C
B1
, D
B1
, C
B2
, D
B2
)
The top MOSFET drivers (TG1 and TG2) are driven digitally
between their respective SW and BOOST pin voltages.
The BOOST voltages are biased from floating bootstrap
capacitors C
B1
and C
B2
, which are normally recharged
through external silicon diodes D
B1
and D
B2
when the
respective top MOSFET is turned off. The capacitors are
charged to about 6.3V (about equal to GATEV
CC
) forcing the
V
BOOST1-SW1
and V
BOOST2-SW2
voltages to be about 6.3V.
The boost capacitors C
B1
and C
B2
need to store about 100
times the gate charge required by the top switches M1 and
M4. In most applications, a 0.1μF to 0.47μF, X5R or X7R
dielectric capacitor is adequate. The bypass capacitance
from GATEV
CC
to GND should be at least ten times the
C
B1
or C
B2
capacitance.
Boost Capacitor Charge Control Block: When the LT8705
operates exclusively in the buck or boost region, one of
the top MOSFETS, M1 or M4, can be constantly on. This
prevents the respective bootstrap capacitor, C
B1
or C
B2
,
from being recharged through the silicon diode, D
B1
or
D
B2
. The Boost Capacitor Charge Control block (see Fig-
ure 1) keeps the appropriate BOOST pin charged in these
ca
ses. When the M1 switch is always on (boost region),
current is automatically drawn from the CSPOUT and/or
BOOST2 pins to charge the BOOST1 capacitor as needed.
When the M4 switch is always on (buck region) current
is drawn from the CSNIN and/or BOOST1 pins to charge
the BOOST2 capacitor. Because of this function, CSPIN
and CSNIN should be connected to a potential close