Datasheet

LT8640/LT8640-1
14
Rev.C
For more information www.analog.com
APPLICATIONS INFORMATION
Low EMI PCB Layout
The LT8640/LT8640-1 is specifically designed to minimize
EMI/EMC emissions and also to maximize efficiency when
switching at high frequencies. For optimal performance
the LT8640/LT8640-1 requires the use of multiple V
IN
bypass capacitors.
Two small 1µF capacitors should be placed as close as
possible to the LT8640/LT8640-1: One capacitor should
be tied to V
IN1
/GND1; a second capacitor should be tied
to V
IN2
/GND2. A third capacitor with a larger value, 2.2µF
or higher, should be placed near V
IN1
or V
IN2
.
See Figure1 for a recommended PCB layout.
For more detail and PCB design files refer to the Demo
Board guide for the LT8640/LT8640-1.
Note that large, switched currents flow in the LT8640/
LT8640-1 V
IN1
, V
IN2
, GND1, and GND2 pins and the input
capacitors (C
IN1
, C
IN2
). The loops formed by the input
capacitors should be as small as possible by placing the
capacitors adjacent to the V
IN1/2
and GND1/2 pins. Capaci-
tors with small case size such as 0603 are optimal due to
lowest parasitic inductance.
The input capacitors, along with the inductor and output
capacitors, should be placed on the same side of the
circuit board, and their connections should be made on
that layer. Place a local, unbroken ground plane under the
application circuit on the layer closest to the surface layer.
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB and RT nodes small so that the ground
traces will shield them from the SW and BOOST nodes.
Figure1. Recommended PCB Layout for the LT8640/LT8640-1
V
V
V
V
V
1
6
11
16
GROUND PLANE
ON LAYER 2
20
R1
R2
C
VCC
C
BST
C
IN1
C
IN2
C
IN3
C
OUT
L
R
T
C
SS
C1 R
PG
17
7 10
22
21
GROUND VIA V
IN
VIA V
OUT
VIA OTHER SIGNAL VIAS
8640 F01
V
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