Datasheet

LT8620
18
8620fa
For more information www.linear.com/LT8620
APPLICATIONS INFORMATION
Figure 4b. Recommended PCB Layout for the
LT8620 QFN Package
Figure 4a. Recommended PCB Layout for the
LT8620 MSOP Package
small so that the ground traces will shield them from the
SW and BOOST nodes. The exposed pad on the bottom of
the package must be soldered to ground so that the pad
is connected to ground electrically and also acts as a heat
sink
thermally. To keep thermal resistance low, extend the
ground plane as much as possible, and add thermal vias
under and near the LT8620 to additional ground planes
within the circuit board and on the bottom side.
High Temperature Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT8620. The exposed pad on the
bottom of the package
must be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread heat dissipated by the LT8620.
Placing additional vias can reduce thermal resistance
further. The maximum load current should be derated
as the ambient temperature approaches the maximum
junction rating. Power dissipation within the LT8620 can
be estimated by
calculating the total power loss from an
efficiency measurement and subtracting the inductor loss.
The die temperature is calculated by multiplying the LT8620
power dissipation by the thermal resistance from junction
to ambient. The LT8620 will stop switching and indicate
a fault condition if safe junction temperature is exceeded.
V
OUT
8620 F04
OUTLINE OF LOCAL
GROUND PLANE
SW
BST
BIAS
INTV
CC
GND
9
10
11
12
13
14
15 PG
FB
GND
V
OUT
16
SYNC
TR/SS
RT
EN/UV
V
IN
1
2
3
4
5
6
7
8
V
OUT
LINE TO BIAS VIAS TO GROUND PLANE
V
OUT
8620 F04
OUTLINE OF LOCAL
GROUND PLANE
SW
GND NC NC NC
NC NC NC NC
BST
BIAS
INTV
CC
GND
13
14
15
16
17
18
19 PG
FB
GND
V
OUT
20
SYNC
TR/SS
RT
EN/UV
V
IN
1
2
3
4
5
6
7
8
V
OUT
LINE TO BIAS VIAS TO GROUND PLANE
9 10 11 12
24 23 22 21
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