Datasheet

LT8612
17
8612fa
For more information www.linear.com/LT8612
APPLICATIONS INFORMATION
Figure 3. Reverse V
IN
Protection
Figure 4. Recommended PCB Layout for the LT8612
the V
IN
pin is grounded while the output is held high,
regardless of EN, parasitic body diodes inside the LT8612
can pull current from the output through the SW pin and
the V
IN
pin. Figure 3 shows a connection of the V
IN
and
EN/UV pins that will allow the LT8612
to run only when
the input voltage is present and that protects against a
shorted or reversed input.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 4 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents flow in the LT8612’s V
IN
pins, PGND pins, and
the input capacitor (C1). The loop formed by the input
capacitor should be as small as possible by placing the
capacitor adjacent to the V
IN
and PGND pins. When using
a physically large input capacitor the resulting loop may
become too large in which case using a small case/value
capacitor placed close to the V
IN
and PGND pins plus a
larger capacitor further away is preferred. These com-
ponents, along with the inductor and output capacitor,
should be placed on the same side of the cir
cuit board,
and their connections should be made on that layer. Place
a local, unbroken ground plane under the application cir-
cuit on the layer closest to the surface layer. The SW and
BOOST nodes should be as small as possible. Finally, keep
the FB and RT nodes small so that the ground traces will
shield them from the SW and BOOST nodes. The exposed
pad on the bottom of the package must be soldered to
ground so that the pad is connected to ground electrically
and also acts as a heat sink thermally. To keep thermal
resistance low, extend the ground plane as much as pos-
sible, and add thermal vias under and near the LT8612 to
additional ground planes within the circuit board and on
the bottom side.
High Temperature Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT8612. The exposed pad on the bottom of the package
must be soldered to a ground plane. This ground should be
tied to large copper layers below with thermal vias; these
layers will spread heat dissipated by the LT8612. Placing
additional vias can reduce thermal resistance further. The
maximum load current should be derated as the ambient
temperature approaches the maximum junction rating.
Power dissipation within the LT8612 can be estimated by
calculating the total power loss from an efficiency mea-
surement and subtracting the inductor loss. The die tem-
perature is calculated by multiplying the LT8612 power
dissipation by the thermal resistance from junction to
ambient. The LT8612 will stop switching and indicate a
fault condition if safe junction temperature is exceeded.
V
IN
V
IN
D1
LT8612
EN/UV
8612 F03
GND
V
OUT
8612 F04
OUTLINE OF LOCAL
GROUND PLANE
SW
BST
BIAS
INTV
CC
GND
17
16
15
18
19
20
21
22
23 PG
FB
GND
V
OUT
24
SYNC
TR/SS
RT
EN/UV
V
IN
1
2
3
4
5
6
7
8
9
10
11 12 13 14
28 27 26 25
V
OUT
LINE TO BIAS VIAS TO GROUND PLANE
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