Datasheet

LT8610
17
8610fa
For more information www.linear.com/LT8610
APPLICATIONS INFORMATION
Figure 3. Reverse V
IN
Protection
V
IN
V
IN
D1
LT8610
EN/UV
8610 F03
GND
Figure 4. Recommended PCB Layout for the LT8610
V
OUT
8610 F04
OUTLINE OF LOCAL
GROUND PLANE
SW
BST
BIAS
INTV
CC
GND
9
10
11
12
13
14
15 PG
FB
GND
V
OUT
16
SYNC
TR/SS
RT
EN/UV
V
IN
1
2
3
4
5
6
7
8
V
OUT
LINE TO BIAS VIAS TO GROUND PLANE
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 4 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
flow in the LT8610’s V
IN
pins, PGND pins, and the input ca-
pacitor (C1). The loop
formed by the input capacitor should
be as small as possible by placing the capacitor adjacent
to the V
IN
and PGND pins. When using a physically large
input capacitor the resulting loop may become too large
in which case using a small case/value capacitor placed
close to the V
IN
and PGND pins plus a larger capacitor
further away is preferred. These components, along with
the inductor and output capacitor, should be placed on the
same side of the circuit board, and their connections should
be made on that layer. Place a local, unbroken ground
plane under the application circuit on the layer closest to
the surface layer. The SW and BOOST nodes should be
as small as possible. Finally, keep the FB and RT nodes
small so that the ground traces will shield them from the
SW and BOOST nodes. The exposed pad on the bottom
of
the package must be soldered to ground so that the pad
is connected to ground electrically and also acts as a heat
sink thermally. To keep thermal resistance low, extend the
ground plane as much as possible, and add thermal vias
under and near the LT8610 to additional ground planes
within the circuit board and on the bottom side.
High Temperature Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT8610. The exposed pad on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread heat dissipated by the LT8610.
Placing additional vias can reduce thermal resistance
further. The maximum load current should be derated
as the ambient temperature approaches the maximum
junction rating. Power dissipation within the LT8610 can
be estimated by calculating the total power loss from an
efficiency measurement and subtracting the inductor loss.
The die temperature is calculated by multiplying the LT8610
power dissipation by the thermal resistance from junction
to ambient. The LT8610 will stop switching and indicate
a
fault condition
if safe junction temperature is exceeded.