Datasheet

LT8609/LT8609A/LT8609B
19
Rev. H
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V
IN
V
IN
LT8609
GND
D1
8609 F03
EN/UV
Figure3. Reverse V
IN
Protection
APPLICATIONS INFORMATION
8609 F04
GND VIA V
IN
VIA V
OUT
VIA EN/UV VIA OTHER SIGNAL VIA
C
OUT
C
IN
C
BST
C
VCC
GROUND PLANE ON LAYER 2
R
T
L
1
C
IN
(OPT)
R1
C
FF
R2
R4
R3
R
PG
C
SS
Figure4. PCB Layout
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure4 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents flow in the LT8609/LT8609A/LT8609B’s V
IN
pins, GND pins, and the input capacitor (C
IN
). The loop
formed by the input capacitor should be as small as
possible by placing the capacitor adjacent to the V
IN
and
GND pins. When using a physically large input capacitor
the resulting loop may become too large in which case
using a small case/value capacitor placed close to the
V
IN
and GND pins plus a larger capacitor further away
is preferred. These components, along with the induc-
tor and output capacitor, should be placed on the same
side of the circuit board, and their connections should
be made on that layer. Place a local, unbroken ground
plane under the application circuit on the layer closest
to the surface layer. The SW and BOOST nodes should
be as small as possible. Finally, keep the FB and RT
nodes small so that the ground traces will shield them
from the SW and BOOST nodes. The exposed pad on the
bottom of the package must be soldered to ground so
that the pad is connected to ground electrically and also
acts as a heat sink thermally. To keep thermal resistance
low, extend the ground plane as much as possible, and
add thermal vias under and near the LT8609/LT8609A/
LT8609B to additional ground planes within the circuit
board and on the bottom side.
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