Datasheet

LT6660
11
6660fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
2.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (W-TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
BOTTOM VIEW—EXPOSED PAD
1.00 ± 0.05
(2 SIDES)
1.35 ± 0.05
(2 SIDES)
0.75 ±0.05
0.40 ±0.05
0.70 ±0.05
1
3
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DC3) DFN 1205 REV Ø
0.25 ± 0.05
R = 0.05
TYP
R = 0.115 TYP
0.50 BSC
0.25 ± 0.05
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.00 ±0.05
(2 SIDES)
1.30 ±0.05
2.00 ±0.05
PACKAGE
OUTLINE
0.50 BSC
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
DC Package
3-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1717 Rev Ø)