Datasheet

LT6220/LT6221/LT6222
14
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applicaTions inForMaTion
A pair of complementary common emitter stages Q14/Q15
that enable the output to swing from rail-to-rail construct
the output stage. The capacitors C2 and C3 form the local
feedback loops that lower the output impedance at high
frequency. These devices are fabricated by Linear Tech
-
nology’s proprietar
y
high speed complementary bipolar
process.
Power Dissipation
The LT6222, with four amplifiers, is housed in a small
16-lead SSOP package and typically has a thermal resis
-
tance (θ
JA
) of 135°C/W. It is necessary to ensure that the
die’s junction temperature does not exceed 150°C. The
junction temperature, T
J
, is calculated from the ambi-
ent temperature,
T
A
, power dissipation, P
D
, and thermal
resistance, θ
JA
:
T
J
= T
A
+ (P
D
• θ
JA
)
The power dissipation in the IC is the function of the sup-
ply voltage
, output voltage and the load resistance. For
a
given supply voltage, the worst-case power dissipation
P
D(MAX)
occurs when the maximum supply current and
the output voltage is at half of either supply voltage for a
given load resistance. P
D(MAX)
is given by:
P
D(MAX)
= V
S
•I
S(MAX)
( )
+
V
S
2
⎛
⎝
⎜
⎞
⎠
⎟
2
/ R
L
Example: For an LT6222 in a 16-lead SSOP package
operating on ±5V supplies and driving a 100Ω load, the
worst-case power dissipation is given by:
P
D(MAX)
/Amp = 10 • 1.8mA
( )
+ 2.5
( )
2
/ 10
0
= 0.018+ 0.0625 = 80.5mW
If all four amplifiers are loaded simultaneously, then the
total power dissipation is 322mW.
The maximum ambient temperature at which the part is
allowed to operate is:
T
A
= T
J
– (P
D(MAX)
• 135°C/W)
= 150°C – (0.322W • 135°C/W) = 106.5°C
Input Offset Voltage
The offset voltage will change depending upon which input
stage is active. The PNP input stage is active from the nega-
tive supply
rail to 1.2V below the positive supply rail, then
the
NPN input stage is activated for the remaining input
range up to the positive supply rail during which the PNP
stage remains inactive. The offset voltage is typically less
than 70µV in the range that the PNP input stage is active.
Input Bias Current
The LT6220/LT6221/LT6222 employ a patent pending
technique to trim the input bias current to less than 150nA
for the input common mode voltage of 0.2V above the
negative supply rail to 1.2V below the positive rail. The
low input offset voltage and low input bias current of the
LT6220/LT6221/LT6222 provide precision performance
especially for high source impedance applications.
Output
The LT6220/LT6221/LT6222 can deliver a large output cur
-
rent, so the short-circuit current limit is set around 50mA
to prevent damage to the device. Attention must be paid to
keep the junction temperature of the IC below the absolute
maximum rating of 150°C (refer to the Power Dissipation
section) when the output is in continuous short circuit.
The output of the amplifier has reverse-biased diodes
connected to each supply. If the output is forced beyond
either supply, unlimited current will flow through these
diodes. If the current is transient and limited to several
hundred milliamperes, no damage will occur to the device.
Overdrive Protection
When the input voltage exceeds the power supplies, two
pair of crossing diodes, D1 to D4, will prevent the output
from reversing polarity. If the input voltage exceeds ei
-
ther power
supply by 700mV, diode D1/D2 or D3/D4 will
turn
on to keep the output at the proper polarity. For the
phase reversal protection to perform properly, the input
current must be limited to less than 5mA. If the amplifier