Datasheet

LT6220/LT6221/LT6222
13
622012fb
For more information www.linear.com/LT6220/LT6221/LT6222
Typical perForMance characTerisTics
±5V Large-Signal Response ±5V Small-Signal Response Output Overdriven Recovery
applicaTions inForMaTion
Q4
Q18Q17
Q16
Q6
Q3
Q7
Q1
Q15
OUT
Q2
Q11
Q12
Q9
Q5 V
BIAS
I
1
D2
D1
D5
D4
D3
D6
D7
D8
ESDD2ESDD1
+IN
–IN
V
–
ESDD3ESDD4
V
+
V
+
V
–
R2R1
R3 R4 R5
622012 F01
+
I
2
+
I
3
C2
C
C
V
–
+
C1
BUFFER
AND
OUTPUT BIAS
V
+
V
–
Q19
Q14
Q8
Q13
Q10
Circuit Description
The LT6220/LT6221/LT6222 have an input and output
signal range that covers from the negative power supply
to the positive power supply. Figure 1 depicts a simplified
schematic of the amplifier. The input stage comprises
two differential amplifiers, a PNP stage, Q1/Q2, and an
NPN stage, Q3/Q4, that are active over different ranges
of common mode input voltage. The PNP stage is active
between the negative supply to approximately 1.2V below
the positive supply. As the input voltage moves closer
toward the positive supply, the transistor Q5 will steer the
tail current, I
1
, to the current mirror, Q6/Q7, activating the
NPN differential pair and the PNP pair becomes inactive
for the rest of the input common mode range up to the
positive supply. Also, at the input stage, devices Q17 to
Q19 act to cancel the bias current of the PNP input pair.
When Q1/Q2 are active, the current in Q16 is controlled
to be the same as the current Q1/Q2. Thus, the base cur
-
rent of Q16 is nominally equal to the base current of the
input
devices. The base current of Q16 is then mirrored by
devices Q17-Q19 to
cancel the base current of the input
devices Q1/Q2.
Figure 1. LT6220/LT6221/LT6222 Simplified Schematic Diagram
0V
2V/DIV
200ns/DIV
622012 G38
V
S
= ±5V
A
V
= 1
R
L
= 1k
0V
50mV/DIV
50ns/DIV
622012 G39
V
S
= ±5V
A
V
= 1
R
L
= 1k
0V
0V
V
IN
1V/DIV
V
OUT
2V/DIV
200ns/DIV
622012 G40
V
S
= 5V, 0V
A
V
= 2
R
L
= 1k