Datasheet

LT6015/LT6016/LT6017
13
601567fd
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applicaTions inForMaTion
Supply Voltage
The positive supply pin of the LT6015/LT6016/LT6017
should be bypassed with a small capacitor (typically 0.1μF)
as close to the supply pins as possible. When driving
heavy loads an additional 4.7μF electrolytic capacitor
should be added. When using split supplies, the same is
true for the V
–
supply pin.
The LT6017 consists of two dual amplifier dice assembled
in a single DFN package which share a common substrate
(V
–
). While the V
–
pins of the quad (pins 16 and 18) must
always be tied together and to the exposed pad underneath,
the V
+
power supply pins (pins 5 and 7) may be supplied
independently. The B and C channel amplifiers are supplied
through V
+
by pin 7, and the A and D channel amplifiers are
supplied by pin 5. If pin 5 and pin 7 are not tied together
and are biased independently, each V
+
pin should have
their own dedicated supply bypass to ground.
Shutdown
While there are no dedicated shutdown pins for the LT6015/
LT6016/LT6017, the amplifiers can effectively be shut down
into a low power state by removing V
+
. In this condition
the input bias current is typically less than 1nA with the
inputs
biased between V
–
and 76V above V
–
, and if the
inputs are taken below V
–
, they appear as a diode in series
with 1k of resistance. The output may be pulled up to 50V
above the V
+
power supply in this condition (See Figure 1).
Pulling the output pin below V
–
will produce unlimited
current and can damage the part.
Reverse Battery
The LT6015/LT6016/LT6017 are protected against reverse
battery voltages up to 50V. In the event a reverse battery
condition occurs, the supply current is typically less
than 5µA (assuming the inputs are biased within a diode
drop from V
–
). For typical single supply applications with
ground referred loads and feedback networks, no other
precautions are required. If the reverse battery condition
results in a negative voltage at the input pins, the current
into the pin should be limited by an external resistor to
less than 10mA.
Inputs
Referring to the Simplified Schematic, the LT6015/LT6016/
LT6017 has two input stages: a common emitter differential
input stage consisting of PNP transistors Q1 and Q2 which
operate when the inputs are biased between V
–
and 1.5V
below V
+
, and a common base input stage consisting of
PNP transistors Q3 to Q6 which operate when the common
mode input is biased greater than V
+
–1.5V. This results
in two distinct operating regions as shown in Figure 2.
For common mode input voltages approximately 1.5V or
more below the V
+
supply (Q1 and Q2 active), the com-
mon emitter PNP input stage is active and the input bias
current
is typically under ±2nA. When the common mode
input is within approximately 1V of the V
+
supply or higher
Figure 1. LT6015/LT6016/LT6017 Fault Tolerant Conditions
INPUTS DRIVEN ABOVE
SUPPLY TOLERANT
5V
–
+
OK!
80V
+
REVERSE BATTERY
TOLERANT
–50V
–
+
OK!
INPUTS DRIVEN BELOW
GROUND TOLERANT
25V
TRANSIENT
5V
–
+
OK!
LARGE DIFFERENTIAL
INPUT VOLTAGE
TOLERANT
5V
–
+
OK!
80V
+
OUTPUT DRIVEN ABOVE THE
V
+
SUPPLY (IN SHUTDOWN)
TOLERANT
0V
–
+
OK!
601567 F01
50V
+
–
+