Datasheet

LT4275
5
4275f
pin FuncTions
IEEEUVLO (Pin 1): Hot Swap Turn-on Threshold Level
Control. Connect to ground for IEEE compliant turn-on
and turn-off (UVLO) voltage thresholds. Leave open for
lower turn-on and turn-off voltage thresholds.
AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive
divider from the auxiliary power input to set the voltage
at which the auxiliary supply takes over. Asserting AUX
pulls down HSGATE, disconnects the signature resistor,
disables classification and floats the PWRGD pin. The
AUX pin sinks I
AUXH
when below its threshold voltage of
V
AUXT
to provide hysteresis. Tie to GND when not used.
RCLASS (Pin 3): Programmable PoE Classification Resis-
tor. See Table 1.
RCLASS
++
(Pin 4, LT4275A Only): Programmable
LTPoE
++
Classification Resistor. This pin is not connected
on the LT4275B/LT4275C. See Table 1.
GND (Pin 5): Ground Pin. Must be soldered to PCB GND.
T2P (Pin 6, LT4275A/LT4275B Only): PSE Type Indica-
tor, Open-Drain Output. T2P floats for a 13W PSE. T2P
pulls down for a 25.5W PSE. T2P pulls down at f
T2P
with
a 50% (typical) duty cycle to indicate the presence of an
LTPoE
++
PSE. T2P is valid after PWRGD is active. This pin
is
not connected on the LT4275C. See the Applications
Information section for behavior when using the AUX pin.
PWRGD (Pin 7): Power Good Indicator, Open-Drain Output.
Pulls down during V
CLASS
and inrush.
HSSRC (Pin 8): External Hot Swap MOSFET Source. Con-
nect to source of the external MOSFET.
HSGATE (Pin 9): External Hot Swap MOSFET Gate Control,
Output. Connect to gate of the external MOSFET.
VPORT (Pin 10): PD interface upper power rail and external
Hot Swap MOSFET drain connection.
Exposed Pad (Pin 11, DFN Package Only): GND. Must
be soldered to PCB GND.
block DiagraM
4275 BD
CONTROL
LOGIC
CLASSIFICATION
LOGIC
VOLTAGE AND
CURRENT REFERENCES
CHARGE
PUMP
OVERTEMP
ON
GND
V
PORT
V
PORT
V
GOC
6.3V
1.4V 1.4V
+
–
+
–
EN
+
–
EN
V
PORT
VPORT
AUX
RCLASS
RCLASS++
T2P
HSSRC
HSGATE
PWRGD
IEEEUVLO