Datasheet

LT4256-3
14
42563fa
APPLICATIO S I FOR ATIO
WUU
U
Therefore, using RETRY only, the LT4256-3 will either
latch off after an overcurrent fault condition or it will go
into a hiccup mode.
Power Good Detection
The LT4256-3 includes a comparator for monitoring the
output voltage. The output voltage is sensed through the
FB pin via an external resistor string. The comparator’s
output (PWRGD) is an open collector capable of operating
from a pull-up as high as 80V.
PWRGD can be used to directly enable/disable a power
module with an active high enable input. Figure 12 shows
how to use PWRGD to control an active low enable input
power module. Signal inversion is accomplished by tran-
sistor Q2 and R10.
The thresholds for the FB pin are 4.45V (low to high) and
3.99V (high to low). To calculate the PWRGD thresholds,
use the following equations:
R
V
kRR k
V
8=
V
• R9, high to low (7)
(8a)
= 4.45V 1+
R8
R9
, low to high (8b)
THPWRGD
THPWRGD
399
1
20 8 9 200
.
–
⎛
⎝
⎜
⎞
⎠
⎟
Ω≤ + ≤Ω
⎛
⎝
⎜
⎞
⎠
⎟
OPEN Pin/Open FET Detection
OPEN is an output which signals abnormally low load
currents. When the voltage across the sense resistor is
less than 3mV, the open collector pull-down device is shut
off allowing OPEN to be externally pulled high. OPEN is
always active when V
CC
is above 9.8V. If V
CC
is below 9.8V
(the internal UVLO threshold), OPEN is pulled low.
Open-circuit MOSFETs are detected with the LT4256-3 by
monitoring the voltage across R5 with OPEN while moni-
toring the output voltage with PWRGD. An open FET
condition is signalled when OPEN is high and PWRGD is
low (after the part has completed its start-up cycle).
Figure 12. Active Low Enable PWRGD Application
4256 F12
R5
100mΩ
LT4256-3
SENSE
13
10
5
7
8
16 15
1
2
4
9
V
CC
GATE
FB
12
V
OUT
PWRGD
RETRY
UV
OV
TIMER
GND
V
CC
24V
(SHORT PIN)
Q1
IRFZ34VS
D1
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
R1
32.4k
R7
100Ω
R6
10Ω
V
OUT
24V
400mA
V
LOGIC
R4
27k
R8
14k
C
L
R10
51k
C2
33nF
C3
0.01µF
C1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
R9
4.02k
Q2
ZN3904
PWRGD
GND
D2
SMAT70A
+