Datasheet

LT4256-3
10
42563fa
APPLICATIO S I FOR ATIO
WUU
U
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge.
The transient currents can permanently damage the con-
nector pins and glitch the system supply, causing other
boards in the system to reset.
The LT4256-3 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The
device also provides undervoltage and overvoltage as well
as overcurrent protection while a power good output
signal indicates when the output supply voltage is ready
with a high output.
Power-Up Sequence
An external N-channel MOSFET pass transistor (Q1) is
placed in the power path to control the power up of the
supply voltage (Figure 5). Resistor R5 provides current
detection and capacitor C1 controls the GATE slew rate.
Resistor R7 compensates the current control loop while
R6 prevents high frequency oscillations in Q1.
When the power pins first make contact, transistor Q1 is
held off. If the voltage on V
CC
is between the externally
programmed undervoltage and overvoltage thresholds,
V
CC
is above 9.8V and the voltage on TIMER is less than
4.65V (typ), transistor Q1 will be turned on (Figure 6). The
voltage on GATE rises with a slope equal to 32µA/C1 and
the supply inrush current is set at:
I
INRUSH
= C
L
• 32µA/C1 (1)
where C
L
is the total load capacitance.
Figure 5. 1.6A, 48V Latchoff Application
Figure 6. Start-Up Waveforms
4256 F05
R5
0.025Ω
LT4256-3
SENSE
13
12
10
5
7
8
16 15
1
2
4
9
V
CC
GATE
V
OUT
FB
PWRGD
RETRY
UV
OV
TIMER
GND
V
IN
48V
GND
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
R1
64.9k
R7
100Ω
R9
4.02k
R6
10Ω
R8
36.5k
PWRGD
V
OUT
48V
1.6A
R4
51k
C
L
C2
33nF
C3
0.01µF
C1
10nF
OPEN
UV = 36V
OV = 73V
PWRGD = 40V
D2
SMAT70A
+
I
OUT
500mA/DIV
V
OUT
50V/DIV
5ms/DIV
4256 F06
PWRGD
50V/DIV
GATE
50V/DIV
C
L
= 125µF