Datasheet

LT4256-1/LT4256-2
8
425612fa
TEST CIRCUIT
TI I G DIAGRA S
WUW
Figure 2. UV to GATE Timing
Figure 3. V
OUT
to PWRGD Timing
Figure 4. SENSE to GATE Timing
Figure 1
V
CC
GATE
SENSE
TIMER
PWRGD
FB
UV
48V
48k
GND
4256 F01
100pF
+
–
UV
4256 F02
GATE
V
OUT
+2V
t
PLHUV
4V
V
OUT
+2V
t
PHLUV
3.6V
V
CC
– SENSE
4256 F04
GATE
V
CC
t
PHLSENSE
55mV
APPLICATIO S I FOR ATIO
WUU
U
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge.
The transient currents can permanently damage the con-
nector pins and glitch the system supply, causing other
boards in the system to reset.
The LT4256-1/LT4256-2 are designed to turn on a board’s
supply voltage in a controlled manner, allowing the board
to be safely inserted or removed from a live backplane. The
device also provides undervoltage as well as overcurrent
protection while a power good output signal indicates
when the output supply voltage is ready with a high output.
Power-Up Sequence
An external N-channel MOSFET pass transistor (Q1) is
placed in the power path to control the power up of the
supply voltage (Figure 5). Resistor R5 provides current
detection and capacitor C1 controls the GATE slew rate.
Resistor R7 compensates the current control loop while
R6 prevents high frequency oscillations in Q1.
FB
4256 F03
PWRGD
1V
t
PLHFB
4.45V
1V
t
PHLFB
3.99V