Datasheet

LT4256-1/LT4256-2
12
425612fa
APPLICATIO S I FOR ATIO
WUU
U
Figure 12. Active Low Enable PWRGD Application
4256 F11
R5
100mΩ
LT4256-1/
LT4256-2
SENSE
6
2
3
4
87
1
5
V
CC
GATE
FB
PWRGD
UV
TIMER
GND
V
IN
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
R1
64.9k
R7
100Ω
R6
10Ω
V
OUT
V
LOGIC
R4
27k
R8
36.5k
C
L
R10
27k
C2
33nF
C3
0.1µF
C1
10nF
R9
4.02k
Q2
2N3904
PWRGD
GND
D2
SMAT70A
UV = 36V
PWRGD = 40V
Power Good Detection
The LT4256-1/LT4256-2 includes a comparator for moni-
toring the output voltage. The output voltage is sensed
through the FB pin via an external resistor string. The
comparator’s output (PWRGD) is an open collector ca-
pable of operating from a pull-up as high as 80V.
PWRGD can be used to directly enable/disable a power
module with an active high enable input. Figure 12 shows
how to use PWRGD to control an active low enable input
power module. Signal inversion is accomplished by tran-
sistor Q2 and R10.
4256 F07
R5
0.010Ω
LT4256-1/
LT4256-2
SENSE
6
3
4
78
1
5
V
CC
GATE
FB
2
PWRGD
UV
TIMER
GND
V
IN
48V
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
Q2
VN2222
R1
64.9k
R7
100Ω
R9
4.02k
R6
10Ω
R8
36.5k
V
OUT
48V
4A
R4
51k
C
L
C2
33nF
C3
0.01µF
OFF SIGNAL
FROM MPU
C1
10nF
GND
D2
SMAT70A
UV = 36V
PWRGD = 40V
Figure 11. How to Use a Logic Signal to Control LT4256 Turn-On/-Off
The thresholds for the FB pin are 4.45V (low to high) and
3.99V (high to low). To calculate the PWRGD thresholds,
use the following equations:
R
V
kRR k
V
8=
V
• R9, high to low (7)
(8a)
= 4.45V 1+
R8
R9
, low to high (8b)
THPWRGD
THPWRGD
399
1
20 8 9 200
.
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