Datasheet

LT4250L/LT4250H
7
4250lhfa
TEST CIRCUIT
TIMING DIAGRAM
PWRGD/PWRGD V
DD
V
+
5V
OV
V
DRAIN
48V
R
5k
DRAIN
LT4250L/LT4250H
UV GATE
V
EE
SENSE
V
SENSE
4250 F01a
V
UV
V
OV
+
–
PWRGD/PWRGD V
DD
OV
48V
20V
DRAIN
LT4250L/LT4250H
UV GATE
V
EE
SENSE
4250 F01b
V
UV
0.1μF
+
–
+
–
10k
10Ω
10Ω
IRF530
Figure 1a. Test Circuit 1 Figure 1b. Test Circuit 2
2V
1V
4250 F02
t
PHLOV
1.255V
0V
OV
GATE
1V
1.235V
t
PLHOV
2V
1V
4250 F03
t
PHLUV
1.125V
0V
UV
GATE
1V
1.255V
t
PLHUV
1V
4250 F04a
t
PHLSENSE
60mV
SENSE
GATE
100mV
V
EE
1V
4250 F04b
t
PHLCB
UV
GATE
1V
4250 F05a
V
PWRGD
– V
DRAIN
= 0V
DRAIN
PWRGD
1V
1.4V
V
EE
DRAIN
PWRGD
1V
1.4V
t
PHLDL
t
PHLDL
V
EE
V
EE
4250 F05b
V
PWRGD
– V
DRAIN
= 0
GATE
PWRGD
1V
1.4V
1.4V
V
EE
GATE
PWRGD
1V
t
PHLGH
t
PHLGH
ΔV
GATE
– V
GATE
= 0
ΔV
GATE
– V
GATE
= 0
Figure 2. OV to GATE Timing Figure 3. UV to GATE Timing
Figure 4a. SENSE to GATE Timing Figure 4b. Active Current Limit Timeout
Figure 5a. DRAIN to PWRGD/PWRGD Timing Figure 5b. GATE to PWRGD/PWRGD Timing