Datasheet

10
LT4220
4220f
TI I G DIAGRA S
WUW
ON
+
4220 F01
GATE
+
0.5V
t
PLHON
+
1V 1V
0V
0V
10V
t
PHLON
+
100mV
Figure 1. ON
+
-to-GATE
+
Timing Figure 2. FB
+
-to-PWRGD Timing
FB
+
4220 F02
PWRGD
2.5V
t
PLHFB
+
1V 1V
2.5V
t
PHLFB
+
0V
0V
100mV
ON
–
0V
V
EE
4220 F03
GATE
–
V
EE
+ 1.2V
–1V
V
EE
+ 3.5V
–1V
t
PHLON
–
t
PLHON
–
FB
–
4220 F04
PWRGD
2.5V
–1V
2.5V
–1V
t
PHLFB
–
t
PLHFB
–
0V
0V
Figure 3. ON
–
-to-GATE
–
Timing Figure 4. FB
–
-to-PWRGD Timing
V
CC
– SENSE
+
4220 F05
GATE
+
10V
t
SENSE
+
100mV
50mV
0V
0V
V
EE
– SENSE
–
0V
4220 F06
GATE
–
–2V
V
EE
t
SENSE
–
–100mV
–50mV
Figure 5. SENSE
+
-to-GATE
+
Timing
Figure 6. SENSE
–
-to-GATE
–
Timing
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
circuit board bypass capacitors can draw large peak
currents from the backplane power bus as they charge up.
The LT4220 is designed to turn on a board’s ±V dual
supplies in a controlled manner, allowing the circuit board
to be safely inserted or removed from a live backplane. The
part provides supply tracking as well as undervoltage and
overcurrent protection. Power good and fault output sig-
nals indicate, respectively, if both power output voltages
are ready or if an overcurrent time-out fault has occurred.
APPLICATIO S I FOR ATIO
WUUU
The dual power supply on the circuit board is controlled
with two external N-channel pass transistors Q1 and Q2 in
the ±V dual power supply path. The sense resistors R
S
+
and R
S
– provide current detection while capacitor C1 and
C2 control the V
OUT
+ and V
OUT
– slew rate. Optionally, the
TRACK pin can be tied to V
CC
enabling the dual output
voltages to ramp up together by tracking the voltages at
the FB
+
and FB
–
pins. Resistors R6 and R8 provide current
control loop compensation while R5 and R7 prevent high
frequency oscillations in Q1 and Q2. C3 and R8 on Q2
prevent fast dV/dt transients from turning Q2 on during