Datasheet

LT3995
12
3995f
For more information www.linear.com/LT3995
APPLICATIONS INFORMATION
clock is 11µA. Holding the SYNC pin DC high yields no
advantages in terms of output ripple or minimum load to
full frequency, so is not recommended.
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistor
values according to:
R1= R2
V
OUT
1.197V
–1






Reference designators refer to the Block Diagram. 1%
resistors are recommended to maintain output voltage
accuracy.
The total resistance of the FB resistor divider should be
selected to be as large as possible to enhance low current
performance. The resistor divider generates a small load
on the output, which should be minimized to optimize the
low supply current at light loads.
When using large FB resistors, a 10pF phase lead capacitor
should be connected from V
OUT
to FB.
Setting the Switching Frequency
The LT3995 uses a constant frequency PWM architecture
that can be programmed to switch from 200kHz to 2MHz
by using a resistor tied from the RT pin to ground. A table
showing the necessary R
T
value for a desired switching
frequency is in Table 1.
Table 1. Switching Frequency vs R
T
Value
SWITCHING FREQUENCY (MHz) R
T
VALUE (kΩ)
0.2 294
0.3 182
0.4 130
0.6 78.7
0.8 54.9
1.0 41.2
1.2 32.4
1.4 26.1
1.6 21.5
1.8 17.8
2.0 14.7
2.2 12.4
To estimate the required R
T
value, use the following
equation:
R
T
=
51.1
f
SW
( )
1.09
– 9.27
where f
SW
is the desired switching frequency in MHz and
R
T
is in kΩ.
Operating Frequency Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, minimum dropout voltage, and
maximum input voltage. The advantage of high frequency
operation is that smaller inductor and capacitor values
may be used. The disadvantages are lower efficiency, and
lower maximum input voltage. The highest acceptable
switching frequency (f
SW(MAX)
) for a given application
can be calculated as follows:
f
SW(MAX)
=
V
OUT
+ V
D
t
ON(MIN)
V
IN
– V
SW
+ V
D
( )
where V
IN
is the typical input voltage, V
OUT
is the output
voltage, V
D
is the catch diode drop (~0.5V), and V
SW
is
the internal switch drop (~0.24V at max load). This equa-
tion shows that slower switching frequency is necessary
to safely accommodate high V
IN
/V
OUT
ratio. This is due
to the limitation on the LT3995’s minimum on-time. The
minimum on-time is a strong function of temperature.
Use the typical minimum on-time curve to design for an
application’s maximum temperature, while adding about
30% for part-to-part variation. The minimum duty cycle that
can be achieved taking minimum on time into account is:
DC
MIN
= f
SW
• t
ON(MIN)
where f
SW
is the switching frequency, the t
ON(MIN)
is the
minimum switch on-time.
A good choice of switching frequency should allow ad-
equate input voltage range (see next two sections) and
keep the inductor and capacitor values small.
Maximum Input Voltage Range
The LT3995 can operate from input voltages of up to 60V.
Often the highest allowed V
IN
during normal operation
(V
IN(OP-MAX)
) is limited by the minimum duty cycle rather