Datasheet

LT3991/LT3991-3.3/LT3991-5
8
3991fa
block DiagraM
+
–
+
–
+
–
OSCILLATOR
200kHz TO 2MHz
Burst Mode
DETECT
V
C
CLAMP
V
C
SLOPE COMP
R
V
IN
V
IN
EN
BOOST
SW
SHDN
SWITCH
LATCH
SS
1µA
V
OUT
C2
C3
C4
L1
D1
BD
RT
R2
GND
ERROR AMP
R1
FB
R
T
C1
PG
1.09V
1V
S
Q
V
OUT
LT3991
ONLY
3991 BD
INTERNAL 1.19V REF
SYNC
R2 R1
Σ
+
–
SHDN
C5
C5
LT3991-3.3
LT3991-5
ONLY
pin FuncTions
PG (Pin 9): The PG pin is the open-drain output of an
internal comparator. PGOOD remains low until the FB pin
is within 9% of the final regulation voltage. PGOOD is
valid when the LT3991 is enabled and V
IN
is above 4.3V.
SYNC (Pin 10): This is the external clock synchronization
input. Ground this pin for low ripple Burst Mode operation
at low output loads. Tie to a clock source for synchroni
-
zation, which will include pulse-skipping at low output
loads. When in pulse-skipping mode, quiescent current
increases to 1.5mA.
GND (Exposed
Pad Pin 11): Ground. The exposed pad
must be soldered to PCB.