Datasheet

LT3988
9
3988f
applicaTions inForMaTion
STEP-DOWN CONSIDERATIONS
FB Resistor Network
The output voltage is programmed with a resistor divider
(refer to the Block Diagram) between the output and the
FB pin. Choose the resistors according to:
R1= R2
V
OUT
750mV
– 1






The parallel combination of R1 and R2 should be 20k or
less to minimize bias current errors. The maximum error
due to V
FB
bias current is ∆V
OUT
= I
FB(MAX)
• R1
Input Voltage Range
The minimum operating voltage is determined either by
the LT3988’s undervoltage lockout or by its maximum
duty cycle. The duty cycle is the fraction of time that the
internal switch is on and is determined by the input and
output voltages:
DC =
V
OUT
+ V
F
V
IN
– V
SW
+ V
F
where V
F
is the forward voltage drop of the catch diode
(~0.4V) and V
SW
is the voltage drop of the internal switch
(~0.3V at maximum load). This leads to a minimum input
voltage of:
V
IN(MIN)
=
V
OUT
+ V
F
DC
MAX
– V
F
+ V
SW
The duty cycle is the fraction of time that the internal
switch is on during a clock cycle. The maximum duty cycle
is generally given by DC
MAX
= 1 – t
OFF(MIN)
• f. However,
unlike most fixed frequency regulators, the LT3988 will not
switch off at the end of each clock cycle if there is sufficient
voltage across the boost capacitor (C3 in Figure1) to fully
saturate the output switch. Forced switch-off for a minimum
time will only occur at the end of a clock cycle when the
boost capacitor needs to be recharged. This operation
has the same effect as lowering the clock frequency for a
fixed off time, resulting in a higher duty cycle and lower
minimum input voltage. The resultant duty cycle depends
on the charging times of the boost capacitor and can be
approximated by the following equation:
DC
MAX
=
B
B+ 1
where B is the switch pin current divided by the typical
boost current from the BOOST pin current vs switch cur-
rent in the Typical Performance Characteristics section.
The maximum operating voltage without pulse-skipping
is determined by the minimum duty cycle DC
MIN
:
V
IN(PS)
=
V
OUT
+ V
F
DC
MIN
– V
F
+ V
SW
with DC
MIN
= t
ON(MIN)
• f.
The LT3988 will regulate the output current at input volt-
ages greater than V
IN(PS)
. Exceeding V
IN(PS)
is safe if the
output is in regulation, if the external components have
adequate ratings to handle the peak conditions and if the
peak inductor current does not exceed 2.3A. A saturating
inductor may further reduce performance. For robust
operation under fault conditions at input voltages of 40V
or greater, use an inductor value of 47µH or larger and a
clock rate of 1MHz or lower.
Both the maximum and minimum input voltages are a
function of the switching frequency and output voltages.
Therefore the maximum switching frequency must be set
to a value that accommodates all the input and output
voltage parameters and must meet both of the following
criteria for each channel:
f
MAX1
=
V
OUT
+ V
F
V
IN(PS)
– V
SW
+ V
F
•
1
t
ON(MIN)
f
MAX2
= 1–
V
OUT
+ V
F
V
IN(MIN)
– V
SW
+ V
F






•
1
t
OFF(MIN)
The values of t
ON(MIN)
and t
OFF(MIN)
are functions of I
SW
and
temperature (see chart in the Typical Performance Character-
istics section). Worst-case values for switch currents greater
than 0.5A are t
ON(MIN)
= 180ns (for T
J
> 125°C t
ON(MIN)
=
200ns) and t
OFF(MIN)
= 240ns. f
MAX1
is the frequency at
which the minimum duty cycle is exceeded. The regulator
will skip ON pulses in order to reduce the overall duty cycle