Datasheet

LT3988
8
3988f
operaTion
The LT3988 is a dual, constant frequency, current mode
regulator with internal power switches. Operation can
be best understood by referring to the Block Diagram in
Figure 1.
If the EN/UVLO pin is pulled low, the LT3988 is shut down
and draws minimal current from the input source(s) tied
to the V
IN
pins. If the EN/UVLO pin exceeds 0.5V (typ),
the internal bias circuits turn on, including the internal
regulator, reference and master oscillator. The switching
regulators will only begin to operate when the EN/UVLO
pin exceeds 1.2V (typ).
The switcher is a current mode regulator. Instead of directly
modulating the duty cycle of the power switch, the feedback
loop controls the peak current in the switch during each
cycle. Compared to voltage mode control, current mode
control improves loop dynamics and provides cycle-by-
cycle current limit.
An oscillator enables an RS flip flop, turning on the internal
power switch. An amplifier and comparator monitor the
current flowing between the V
IN
and SW pins, turning the
switch off when this current reaches a level determined by
the voltage at V
C
. An error amplifier measures the output
voltage through an external resistor divider tied to the
FB pin and servos the V
C
voltage. If the error amplifier’s
output increases, more current is delivered to the output;
if it decreases, less current is delivered. An active clamp
on the V
C
voltage provides a current limit.
The switching frequency is set either by the resistance to
GND at the RT pin or by the frequency of the logic-level
signal driving the SYNC pin. A detection circuit monitors
for the presence of a SYNC signal on the pin and switches
between the two modes upon detection of a clock applied
to the SYNC pin. Use of the SYNC pin as a frequency input
requires the use of an R
T
resistor as well. This requirement
is detailed in the Switching Frequency section. Onboard
circuitry generates the appropriate slope compensation
ramps and generates the 180° out-of-phase clocks for
the two channels.
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
This slave oscillator is normally synchronized to the master
oscillator. A comparator senses when V
FB
is less than 50%
of its regulated value and switches the regulator from the
master oscillator to a slower slave oscillator. V
FB
is less than
50% of its regulated value during start-up, short-circuit,
and overload conditions. Frequency foldback helps limit
switch current under these conditions.
The TRACK/SS pins override the 0.75V reference of the
FB pins when the TRACK/SS pins are below 0.75V. This
allows either coincident or ratiometric supply tracking on
start-up as well as a soft-start capability.
The switch drivers operate either from V
IN
or from the
BOOST pin. An external capacitor and internal Schottky
diode are used to generate a voltage at the BOOST pin that
is higher than the input supply. This allows the driver to
obtain a low V
CE
across the internal bipolar NPN power
switch for efficient operation.
The BD pin serves two purposes. The voltage at BD deter-
mines the BOOST1 and BOOST2 levels over the V
IN1
and
V
IN2
supply voltages, and allows the internal circuitry to
draw its current from a lower voltage supply than V
IN1
.
This reduces power dissipation and increases efficiency.
If the voltage at BD falls below 3V, then quiescent current
will flow from V
IN1
.
The overvoltage and undervoltage detection shuts down
the LT3988 if the input voltage on V
IN1
goes above or
below thresholds. The overvoltage detector shuts down
the regulators when V
IN1
exceeds 60V. An undervoltage
detector monitoring V
IN1
disables both regulators when
V
IN1
is under 3.7V, an undervoltage detector monitoring
V
IN2
shuts down channel 2 when V
IN2
is under 2.5V. The
higher voltage is required on V
IN1
to accomodate internal
bias circuits. Additionally, tying the EN/UVLO pin to a volt-
age divider from V
IN1
to ground allows a programmable
undervoltage threshold.