Datasheet

LT3972
17
3972fa
VIAS TO LOCAL GROUND PLANE
VIAS TO V
OUT
VIAS TO RUN/SS
VIAS TO PG
VIAS TO V
IN
OUTLINE OF LOCAL
GROUND PLANE
3972 F09
L1
C2
R
RT
R
PG
R
C
R2
R1
C
C
V
OUT
D1
C1
GND
VIAS TO SYNC
Figure 9. A Good PCB Layout Ensures Proper, Low EMI Operation
diode (D1) and the input capacitor (C1). The loop formed
by these components should be as small as possible. These
components, along with the inductor and output capacitor,
should be placed on the same side of the circuit board,
and their connections should be made on that layer. Place
a local, unbroken ground plane below these components.
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB and V
C
nodes small so that the ground
traces will shield them from the SW and BOOST nodes.
The Exposed Pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3972 to additional ground planes within the circuit
board and on the bottom side.
APPLICATIONS INFORMATION
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LT3972 circuits. However, these capaci-
tors can cause problems if the LT3972 is plugged into a
live supply (see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor,
combined with stray inductance in series with the power
source, forms an under damped tank circuit, and the
voltage at the V
IN
pin of the LT3972 can ring to twice the
nominal input voltage, possibly exceeding the LT3972’s
rating and damaging the part. If the input supply is poorly
controlled or the user will be plugging the LT3972 into an
energized supply, the input network should be designed
to prevent this overshoot. Figure 10 shows the waveforms
that result when an LT3972 circuit is connected to a 24V
supply through six feet of 24-gauge twisted pair. The
fi rst plot is the response with a 4.7μF ceramic capacitor
at the input. The input voltage rings as high as 50V and
the input current peaks at 26A. A good solution is shown
in Figure 10b. A 0.7Ω resistor is added in series with the
input to eliminate the voltage overshoot (it also reduces
the peak input current). A 0.1μF capacitor improves high
frequency fi ltering. For high input voltages its impact on
effi ciency is minor, reducing effi ciency by 1.5 percent for
a 5V output at full load operating from 24V.
High Temperature Considerations
The PCB must provide heat sinking to keep the LT3972
cool. The Exposed Pad on the bottom of the package must
be soldered to a ground plane. This ground should be tied
to large copper layers below with thermal vias; these lay-
ers will spread the heat dissipated by the LT3972. Place
additional vias can reduce thermal resistance further. With
these steps, the thermal resistance from die (or junction)