Datasheet
LT3959
12
3959fa
For more information www.linear.com/LT3959
Some frequency foldback waveforms are shown in the
Typical Applications section. The frequency foldback func-
tion prevents
I
L
from exceeding the programmed limits
because of the minimum on-time.
During frequency foldback, external clock synchronization
is disabled to allow the frequency reducing operation to
function properly.
Loop Compensation
Loop compensation determines the stability and transient
performance. The LT3959 uses current mode control to
regulate the output which simplifies loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3959, a series resistor-capacitor
network is usually connected from the V
C
pin to SGND.
Figure 1 shows the typical V
C
compensation network. For
most applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range of
5k to 50k. A small capacitor is often connected in paral
-
lel with the RC compensation network to attenuate the
V
C
voltage ripple induced from the output voltage ripple
through the internal error amplifier. The parallel capacitor
usually ranges in value from 10pF to 100pF. A practical
approach to design the compensation
network is to start
with one of the circuits in this data sheet that is similar
to your application, and tune the compensation network
to optimize the performance. Stability should then be
checked across all operating conditions, including load
current, input voltage and temperature.
The Internal Power Switch Current
For control and protection, the LT3959 measures the
internal power MOSFET current by using a sense resistor
(R
SENSE
) between GND and the MOSFET source. Figure 2
shows a typical wave-form of the internal switch current
(I
SW
).
Due to the current limit (minimum 6A) of the internal power
switch, the LT3959 should be used in the applications
that the switch peak current I
SW(PEAK)
during steady state
normal operation is lower than 6A by a sufficient margin
(10% or higher is recommended).
It is recommended to measure the IC temperature in steady
state to verify that the junction temperature limit (125°C) is
not exceeded. A low switching frequency may be required
to ensure T
J(MAX)
does not exceed 125°C.
If LT3959 die temperature reaches thermal lockout
threshold at 165°C (typical), the IC will initiate several
protective actions. The power switch will be turned off.
A soft-start
operation will
be triggered. The IC will be en-
abled again when the junction temperature has dropped
by 5°C (nominal).
APPLICA
TION CIRCUITS
The LT3959 can be configured as different topologies.
The design procedure for component selection differs
somewhat between these topologies. The first topology
to be analyzed will be the boost converter, followed by
SEPIC and inverting converters.
Figure 2. The SW Current During a Switching Cycle
applicaTions inForMaTion
3959 F02
I
SW(PEAK)
∆I
SW
I
SW
t
DT
S
T
S