Datasheet

LT3959
10
3959fa
For more information www.linear.com/LT3959
INTV
CC
Low Dropout Voltage Regulators
The LT3959 features two internal low dropout (LDO) volt-
age regulators
(
V
IN
LDO and DRIVE LDO) powered from
different supplies (V
IN
and DRIVE respectively). Both LDO’s
regulate the internal INTV
CC
supply which powers the gate
driver and the internal loads, as shown in Figure 1. Both
regulators are designed so that current does not flow from
INTV
CC
to the LDO input under a reverse bias condition.
DRIVE LDO regulates the INTV
CC
to 4.75V, while V
IN
LDO
regulates the INTV
CC
to 3.75V. V
IN
LDO is turned off when
the INTV
CC
voltage is greater than 3.75V (typical). Both
LDO’s can be turned off if the INTV
CC
pin is driven by a
supply of 4.75V or higher but less than 8V (the INTV
CC
maximum voltage rating is 8V). A table of the LDO sup-
ply and output voltage combination is shown in Table 1.
Table 1. LDO’s Supply and Output Voltage Combination (Assuming
That the LDO Dropout Voltage is 0.15V)
SUPPLY VOLTAGES LDO OUTPUT
LDO STATUS
(Note 7)
V
IN
DRIVE INTV
CC
V
IN
≤ 3.9V V
DRIVE
< V
IN
V
IN
– 0.15V #1 Is ON
V
DRIVE
= V
IN
V
IN
– 0.15V #1 #2 are ON
V
IN
< V
DRIVE
< 4.9V V
DRIVE
– 0.15V #2 Is ON
4.9V ≤ V
DRIVE
≤ 40V 4.75V #2 Is ON
3.9V < V
IN
≤ 40V V
DRIVE
< 3.9V 3.75V #1 Is ON
V
DRIVE
= 3.9V 3.75V #1 #2 are ON
3.9V < V
DRIVE
< 4.9V V
DRIVE
– 0.15V #2 Is ON
4.9V ≤ V
DRIVE
≤ 40V 4.75V #2 Is ON
Note 7: #1 is V
IN
LDO and #2 is DRIVE LDO
The DRIVE pin provides flexibility to power the gate driver
and the internal loads from a supply that is available only
when the switcher is enabled and running. If not used,
the DRIVE pin should be tied to V
IN
.
The INTV
CC
pin must be bypassed to SGND immediately
adjacent to the INTV
CC
pin with a minimum of 4.7µF ceramic
capacitor. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate driver.
Operating Frequency and Synchronization
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency op
-
eration improves efficiency by reducing gate drive current
and
internal MOSFET and diode switching losses. However,
lower frequency operation requires a physically larger
inductor. Switching frequency also has implications for
loop compensation. The LT3959 uses a constant-frequency
architecture that can be programmed over a 100kHz to
1MHz range with a single external resistor from the RT
pin to SGND, as shown in Figure 1. The RT pin must have
an external resistor to SGND for proper operation of the
LT3959. A table for selecting the value of R
T
for a given
operating frequency is shown in Table 2.
Table 2. Timing Resistor (R
T
) Value
OSCILLATOR FREQUENCY (kHz) R
T
(kΩ)
100 86.6
200 41.2
300 27.4
400 21.0
500 16.5
600 13.7
700 11.5
800 9.76
900 8.45
1000 6.81
The switching frequency of the LT3959 can be synchro-
nized to the positive edge of an external clock source.
By
providing a digital clock signal into the SYNC pin,
the LT3959 will operate at the SYNC clock frequency. If
this feature is used, an R
T
resistor should be chosen to
program a switching frequency 20% slower than SYNC
pulse frequency. The SYNC pulse should have a minimum
pulse width of 200ns. Tie the SYNC pin to SGND if this
feature is not used.
applicaTions inForMaTion