Datasheet

LT3958
22
3958f
APPLICATIONS INFORMATION
• In fl yback confi guration, the high di/dt primary loop
contains the input capacitor, the primary winding,
the internal power MOSFET. The high di/dt second-
ary loop contains the output capacitor, the secondary
winding and the output diode.
• In SEPIC confi guration, the high di/dt loop con-
tains the internal power MOSFET, output capacitor,
Schottky diode and the coupling capacitor.
• In inverting confi guration, the high di/dt loop con-
tains internal power MOSFET, Schottky diode and the
coupling capacitor.
Check the stress on the internal power MOSFET by measur-
ing the SW-to-GND voltage directly across the IC terminals.
Make sure the inductive ringing does not exceed the
maximum rating of the internal power MOSFET (84V).
The small-signal components should be placed away from
high frequency switching nodes. For optimum load regula-
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
the top of the output capacitor (Kelvin connection), staying
away from any high dV/dt traces. Place the divider resis-
tors near the LT3958 in order to keep the high impedance
FBX node short.
Figure 9 shows the suggested layout of the 48V V
OUT
boost
converter (see the Typical Applications section).
3958 F09
LT3958
37
38
12
13 14 15 16 17
36 35 34 33 32 31 30
21
23
24
25
27
28
8
6
4
3
2
1
20
9
10
VIA TO V
OUT
R1
R2
C
SS
R
T
R
C
C
C
C
VCC
R3
R4
D1
L1
C
OUT
C
OUT
C
IN
GND V
OUT
V
IN
VIA TO V
OUT
VIAS TO SGND GROUND PLANE
VIAS TO SW PLANE
Figure 9. Suggested Layout of the 10V to 40V Input, 48V Output Boost Converter