Datasheet

LT3958
13
3958f
APPLICATIONS INFORMATION
The Internal Power Switch Current
For control and protection, the LT3958 measures the
internal power MOSFET current by using a sense resistor
(R
SENSE
) between GND and the MOSFET source. Figure 3
shows a typical waveform of the internal switch current
(I
SW
).
On-Chip Power Dissipation and Thermal Lockout (TLO)
The on-chip power dissipation of LT3958 can be estimated
using the following equation:
P
IC
≈ I
2
SW
• D • R
DS(ON)
+ V
2
SW(PEAK)
• I
SW
• ƒ • 200pF/A +
V
IN
• (1.6mA + ƒ • 10nC)
where R
DS(ON)
is the internal switch on-resistance which
can be obtained from the Typical Performance Characteris-
tics section. V
SW(PEAK)
is the peak switch off-state voltage.
The maximum power dissipation P
IC(MAX)
can be obtained
by comparing P
IC
across all the V
IN
range at the maximum
output current . The highest junction temperature can be
estimated using the following equation:
T
J(MAX)
≈ T
A
+ P
IC(MAX)
• 42°C/W
It is recommended to measure the IC temperature in steady
state to verify that the junction temperature limit is not
exceeded. A low switching frequency may be required to
ensure T
J(MAX)
does not exceed 125°C.
If LT3958 die temperature reaches thermal lockout
threshold at 165°C (typical), the IC will initiate several
protective actions. The power switch will be turned off.
A soft-start operation will be triggered. The IC will be en-
abled again when the junction temperature has dropped
by 5°C (nominal).
Figure 3. The Switch Current During a Switching Cycle
3958 F03
I
SW(PEAK)
$I
SW
I
SW
t
DT
S
T
S
Figure 4. The RC Filter on SENSE1 Pin and SENSE2 Pin
3958 F04
LT3958
R
FLT
C
FLT
SENSE2
SGND
SENSE1
Due to the current limit (minimum 3.3A) of the internal
power switch, the LT3958 should be used in the applica-
tions that the switch peak current I
SW(PEAK)
during steady
state normal operation is lower than 3.3A by a suffi cient
margin (10% or higher is recommended).
The LT3958 switching controller incorporates 100ns
timing interval to blank the ringing on the current sense
signal across R
SENSE
immediately after M1 is turned on.
This ringing is caused by the parasitic inductance and
capacitance of the PCB trace, the sense resistor, the diode,
and the MOSFET. The 100ns timing interval is adequate
for most of the LT3958 applications. In the applications
that have very large and long ringing on the current sense
signal, a small RC fi lter can be added to fi lter out the excess
ringing. Figure 4 shows the RC fi lter on the SENSE1 and
SENSE2 pins. It is usually suffi cient to choose 22 for
R
FLT
and 2.2nF to 10nF for C
FLT
. Keep R
FLT
’s resistance
low. Remember that there is 65µA (typical) fl owing out of
the SENSE2 pin. Adding R
FLT
will affect the internal power
switch current limit threshold:
I
SW _ILIM
= 1−
65µA •R
FLT
48mV
⎛
⎝
⎜
⎞
⎠
⎟
• 3.3A