Datasheet

LT3957A
21
3957afa
APPLICATIONS INFORMATION
IC is essential, especially the power paths with higher di/dt.
The following high di/dt loops of different topologies should
be kept as tight as possible to reduce inductive ringing:
• In boost configuration, the high di/dt loop contains the
output capacitor, the internal power MOSFET and the
Schottky diode.
• In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
internal power MOSFET. The high di/dt secondary loop
contains the output capacitor, the secondary winding
and the output diode.
• In SEPIC configuration, the high di/dt loop contains
the internal power MOSFET, output capacitor, Schottky
diode and the coupling capacitor.
• In inverting configuration, the high di/dt loop contains
internal power MOSFET, Schottky diode and the coupling
capacitor.
Check the stress on the internal power MOSFET by
measuring the SW-to-GND voltage directly across the IC
terminals. Make sure the inductive ringing does not exceed
the maximum rating of the internal power MOSFET (40V).
The small-signal components should be placed away
from high frequency switching nodes. For optimum load
regulation and true remote sensing, the top of the output
voltage sensing resistor divider should connect indepen-
dently to the top of the output capacitor (Kelvin connec-
tion), staying away from any high dV/dt traces. Place the
divider resistors near the LT3957A in order to keep the
high impedance FBX node short.
Figure 9 shows the suggested layout of the 4.5V to16V
input, 24V output boost converter in the Typical Applica-
tion section.
3958A F09
LT3957A
37
38
12
13 14 15 16 17
36 35 34 33 32 31 30
21
23
24
25
27
28
8
6
4
3
2
1
20
9
10
VIA TO V
OUT
R1
R2
C
SS
R
T
R
C
C
C
C
VCC
R3
R4
D1
L1
C
OUT
C
OUT
C
IN
GND V
OUT
V
IN
VIA TO V
OUT
VIAS TO SGND GROUND PLANE
VIAS TO SW PLANE
Figure 9. Suggested Layout of the 4.5V to 16V Input. 24V Output Boost Converter in the Typical Application Section