Datasheet

LT3845A
8
3845afa
TG: The TG pin is the bootstrapped gate drive for the top
N-Channel MOSFET. Since very fast high currents are driven
from this pin, connect it to the gate of the power MOSFET
with a short and wide, typically 0.02” width, PCB trace to
minimize inductance.
V
C
: The V
C
pin is the output of the error amplifier whose
voltage corresponds to the maximum (peak) switch
current per oscillator cycle. The error amplifier is typically
configured as an integrator by connecting an RC network
from the V
C
pin to SGND. This circuit creates the dominant
pole for the converter regulation control loop. Specific
integrator characteristics can be configured to optimize
transient response. When Burst Mode operation is enabled
(see Pin 4 description), an internal low impedance clamp on
the V
C
pin is set at 100mV below the burst threshold, which
limits the negative excursion of the pin voltage. Therefore,
this pin cannot be pulled low with a low impedance source.
If the V
C
pin must be externally manipulated, do so through
a 1kΩ series resistance.
V
CC
: The V
CC
pin is the internal bias supply decoupling
node. Use a low ESR, 1µF or greater ceramic capacitor to
decouple this node to PGND. Most internal IC functions are
PIN FUNCTIONS
powered from this bias supply. An external diode connected
from V
CC
to the BOOST pin charges the bootstrapped
capacitor during the off-time of the main power switch.
Back driving the V
CC
pin from an external DC voltage
source, such as the V
OUT
output of the regulator supply,
increases overall efficiency and reduces power dissipation
in the IC. In shutdown mode this pin sinks 20µA until the
pin voltage is discharged to 0V.
V
FB
: The output voltage feedback pin, V
FB
, is externally
connected to the supply output voltage via a resistive divider.
The V
FB
pin is internally connected to the inverting input
of the error amplifier. In regulation, V
FB
is 1.231V.
V
IN
: The V
IN
pin is the main supply pin and should be
decoupled to SGND with a low ESR capacitor (at least
0.1µF) located close to the pin.
Exposed Pad (SGND) (TSSOP Only): The exposed
leadframe is internally connected to the SGND pin. Solder
the exposed pad to the PCB ground for electrical contact
and optimal thermal performance.