Datasheet

LT3845A
17
3845afa
DV
IN
is typically chosen at a level acceptable to the user.
100mV to 200mV is a good starting point. Aluminum elec-
trolytic capacitors are a good choice for high voltage, bulk
capacitance due to their high capacitance per unit area.
The capacitor’s RMS current is:
I
CIN(RMS)
=I
OUT
V
OUT
(V
IN
– V
OUT
)
(V
IN
)
2
If applicable, calculate it at the worst case condition,
V
IN
= 2V
OUT
. The RMS current rating of the capacitor
is specified by the manufacturer and should exceed the
calculated I
CIN(RMS)
. Due to their low ESR (Equivalent
Series Resistance), ceramic capacitors are a good choice
for high voltage, high RMS current handling. Note that the
ripple current ratings from aluminum electrolytic capacitor
manufacturers are based on 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose a
capacitor rated at a higher temperature than required.
The combination of aluminum electrolytic capacitors and
ceramic capacitors is an economical approach to meeting
the input capacitor requirements. The capacitor voltage
rating must be rated greater than V
IN(MAX)
. Multiple
capacitors may also be paralleled to meet size or height
requirements in the design. Locate the capacitor very close
to the MOSFET switch and use short, wide PCB traces to
minimize parasitic inductance.
Output Capacitor Selection
The output capacitance, C
OUT
, selection is based on the
design’s output voltage ripple, DV
OUT
and transient load
requirements. DV
OUT
is a function of DI
L
and the C
OUT
ESR. It is calculated by:
DV
OUT
= DI
L
• ESR+
1
(8 • f
SW
• C
OUT
)






APPLICATIONS INFORMATION
The maximum ESR required to meet a DV
OUT
design
requirement can be calculated by:
ESR(MAX)=
(DV
OUT
)(L)(f
SW
)
V
OUT
• 1–
V
OUT
V
IN(MAX)








Worst-case DV
OUT
occurs at highest input voltage. Use
paralleled multiple capacitors to meet the ESR requirements.
Increasing the inductance is an option to lower the ESR require-
ments. For extremely low DV
OUT
, an additional LC filter stage
can be added to the output of the supply. Application Note
44 has some good tips on sizing an additional output filter.
Output Voltage Programming
A resistive divider sets the DC output voltage according
to the following formula:
R2= R1
V
OUT
1.231V
– 1






The external resistor divider is connected to the output of
the converter as shown in Figure 3. Tolerance of the feedback
resistors will add additional error to the output voltage.
Example: V
OUT
= 12V; R1 = 10k
R2= 10k
12V
1.231V
−1






= 87.48kΩ −use 86.6k 1%
The V
FB
pin input bias current is typically 25nA, so use
of extremely high value feedback resistors could cause a
converter output that is slightly higher than expected. Bias
current error at the output can be estimated as:
DV
OUT(BIAS)
= 25nA • R2