Datasheet

LT3845A
13
3845afa
Soft-Start
The soft-start function controls the slew rate of the power
supply output voltage during start-up. A controlled output
voltage ramp minimizes output voltage overshoot, reduces
inrush current from the V
IN
supply, and facilitates supply
sequencing. A capacitor, C
SS
, connected from the C
SS
pin to SGND, programs the slew rate. The capacitor is
charged from an internal 2µA current source producing
a ramped voltage. The capacitor voltage overrides the
internal reference to the error amplifier. If the V
FB
pin voltage
exceeds the C
SS
pin voltage then the current threshold set
by the DC control voltage, V
C
, is decreased and the inductor
current is lowered. This in turn decreases the output voltage
slew rate allowing the C
SS
pin voltage ramp to catch up to
the V
FB
pin voltage. An internal 100mV offset is added to
the V
FB
pin voltage relative to the C
SS
pin voltage so that
at start-up the soft-start circuit will discharge the V
C
pin
voltage below the DC control voltage equivalent to zero
inductor current. This will reduce the input supply inrush
current. The soft-start circuit is disabled once the C
SS
pin
voltage has been charged to 200mV above the internal
reference of 1.231V.
During a V
IN
UVLO, V
CC
UVLO or SHDN UVLO event, the
C
SS
pin voltage is discharged with a 50µA current source.
In normal operation the C
SS
pin voltage is clamped to a
diode above the V
FB
pin voltage. Therefore, the value of the
C
SS
capacitor is relevant to how long of a fault event will
retrigger a soft-start. If any of the above UVLO conditions
occur, the C
SS
pin voltage will be discharged with a 50µA
current source. There is a diode worth of voltage headroom
to ride through the fault before the C
SS
pin voltage enters
its active region and the soft-start function is enabled.
Also, since the C
SS
pin voltage is clamped to a diode above
the V
FB
pin voltage, during a short circuit the C
SS
pin voltage
is pulled low because the V
FB
pin voltage is low. Once
the short has been removed the V
FB
pin voltage starts to
recover. The soft-start circuit takes control of the output
voltage slew rate once the V
FB
pin voltage has exceeded
the slowly ramping C
SS
pin voltage, reducing the output
voltage overshoot during a short circuit recovery.
APPLICATIONS INFORMATION
Adaptive Nonoverlap (NOL) Output Stage
The FET driver output stages implement adaptive
nonoverlap control. This feature maintains a constant
dead time, preventing shoot-through switch currents,
independent of the type, size or operating conditions of
the external switch elements.
Each of the two switch drivers contains a NOL control
circuit, which monitors the output gate drive signal of the
other switch driver. The NOL control circuits interrupt the
“turn on” command to their associated switch driver until
the other switch gate is fully discharged.
Shutdown
The LT3845A SHDN pin uses a bandgap generated reference
threshold of 1.35V. This precision threshold allows use of
the SHDN pin for both logic-level controlled applications
and analog monitoring applications such as power supply
sequencing.
The LT3845A operational status is primarily controlled by
a UVLO circuit on the V
CC
regulator pin. When the IC is
enabled via the SHDN pin, only the V
CC
regulator is enabled.
Switching remains disabled until the UVLO threshold is
achieved at the V
CC
pin, when the remainder of the IC is
enabled and switching commences.
Because an LT3845A controlled converter is a power
transfer device, a voltage that is lower than expected on
the input supply could require currents that exceed the
sourcing capabilities of that supply, causing the system
to lock up in an undervoltage state. Input supply start-up
protection can be achieved by enabling the SHDN pin
using a resistive divider from the V
IN
supply to ground.
Setting the divider output to 1.35V when that supply is
at an adequate voltage prevents an LT3845A converter
from drawing large currents until the input supply is able
to provide the required power. 120mV of input hysteresis
on the SHDN pin allows for almost 10% of input supply
droop before disabling the converter.