Datasheet

LT3844
14
3844fb
APPLICATIONS INFORMATION
it advisable to further derate the capacitor or to choose a
capacitor rated at a higher temperature than required.
The combination of aluminum electrolytic capacitors and
ceramic capacitors is an economical approach to meet-
ing the input capacitor requirements. The capacitor volt-
age rating must be rated greater than V
IN(MAX)
. Multiple
capacitors may also be paralleled to meet size or height
requirements in the design. Locate the capacitor very close
to the MOSFET switch and use short, wide PCB traces to
minimize parasitic inductance.
Step-Down Converter: Output Capacitor Selection
The output capacitance, C
OUT
, selection is based on the
design’s output voltage ripple, ΔV
OUT
and transient load
requirements. ΔV
OUT
is a function of ΔI
L
and the C
OUT
ESR. It is calculated by:
Δ=Δ +
⎛
⎝
⎜
⎞
⎠
⎟
VIESR
fC
OUT L
SW OUT
•
(• • )
1
8
The maximum ESR required to meet a ΔV
OUT
design
requirement can be calculated by:
ESR MAX
VLf
V
V
V
OUT SW
OUT
OUT
IN MAX
()
()()()
•–
()
=
Δ
1
⎛⎛
⎝
⎜
⎞
⎠
⎟
Worst-case ΔV
OUT
occurs at highest input voltage. Use
paralleled multiple capacitors to meet the ESR require-
ments. Increasing the inductance is an option to lower
the ESR requirements. For extremely low ΔV
OUT
, an ad-
ditional LC fi lter stage can be added to the output of the
supply. Application Note 44 has some good tips on sizing
an additional output fi lter.
Output Voltage Programming
A resistive divider sets the DC output voltage according
to the following formula:
RR
V
V
OUT
21
1 231
1=
⎛
⎝
⎜
⎞
⎠
⎟
.
–
The external resistor divider is connected to the output
of the converter as shown in Figure 2. Tolerance of the
feedback resistors will add additional error to the output
voltage.
Example: V
OUT
= 12V; R1 = 10k
Rk
V
V
kuse k210
12
1 231
1 8748 866 1=−
⎛
⎝
⎜
⎞
⎠
⎟
=−
.
..%
The V
FB
pin input bias current is typically 25nA, so use
of extremely high value feedback resistors could cause a
converter output that is slightly higher than expected. Bias
current error at the output can be estimated as:
ΔV
OUT(BIAS)
= 25nA • R2
Supply UVLO and Shutdown
The SHDN pin has a precision voltage threshold with
hysteresis which can be used as an undervoltage lockout
threshold (UVLO) for the power supply. Undervoltage
lockout keeps the LT3844 in shutdown until the supply
input voltage is above a certain voltage programmed by
the user. The hysteresis voltage prevents noise from falsely
tripping UVLO.
Resistors are chosen by fi rst selecting R
B
. Then:
RR
V
V
AB
SUPPLY ON
=
⎛
⎝
⎜
⎞
⎠
⎟
•
.
–
()
135
1
L1
V
FB
PIN
R2
R1
V
OUT
C
OUT
3844 F02
SHDN PIN
R
A
R
B
V
SUPPLY
3844 F03
Figure 2. Output Voltage Feedback Divider Figure 3. Undervoltage Lockout Circuit