Datasheet

LT3825
7
3825fe
V
C
(Pin 9): Pin used for frequency compensation for
the switcher control loop. It is the output of the feed-
back amplifier and the input to the current comparator.
Switcher frequency compensation components are
normally placed on this pin to ground. The voltage on
this pin is proportional to the peak primary switch cur-
rent. The feedback amplifier output is enabled during the
synchronous switch-on time.
UVLO (Pin 10): A resistive divider from V
IN
to this pin sets
an undervoltage lockout based upon V
IN
level (not V
CC
).
When the UVLO pin is below its threshold, the gate drives
are disabled, but the part draws its normal quiescent current
from V
CC
. The V
CC
undervoltage lockout supersedes this
function so V
CC
must be great enough to start the part.
The bias current on
this pin has hysteresis such that the
bias current is sourced when the UVLO threshold is ex-
ceeded. This introduces a hysteresis at the pin equivalent
to the bias current change times the impedance of the
upper divider resistor. The user can control the amount
of hysteresis by adjusting the impedance of the divider.
See the Applications Information for details. Tie the UVLO
pin to V
CC
if you are not using this function.
SENSE
–
(Pin 11), SENSE
+
(Pin 12): These pins are used
to measure primary-side switch current through an ex-
ternal sense resistor. Peak primary-side current is used
in the converter control loop. Make Kelvin connections
to the sense resistor to reduce noise problems. SENSE
–
connects to the ground side. At maximum current (V
C
at
its maximum voltage) it
has a 98mV threshold. The signal
is blanked (ignored) during the minimum turn-on time.
C
CMP
(Pin 13): Pin for external filter capacitor for the
optional load compensation function. Load compensation
reduces the effects of parasitic resistances in the feedback
sensing path. A 0.1µF ceramic capacitor suffices for most
applications. Short this pin to GND in less demanding ap-
plications that don’t require load compensation.
R
CMP
(Pin 14): Pin for optional external load compensation
resistor. Use of this pin allows for nominal compensation
of parasitic resistances in the feedback sensing path. In
less demanding applications, this resistor is not needed
and this pin can be left open. See Applications Informa-
tion for details.
PGDLY (Pin 15): Pin for external programming resistor to
set delay from synchronous gate turn-off to primary gate
turn-
on. See Applications Information for details.
PG (Pin 16): Gate Drive Pin for the Primary-Side MOS-
FET Switch. Large dynamic currents flow during voltage
transitions. See the Applications Information for details.
GND (Exposed Pad Pin 17): This is the ground connec-
tion for both signal ground and gate driver grounds. This
GND must be connected to the PCB ground plane. Careful
attention must be paid to ground
layout. See Applications
Information for details.
PIN FUNCTIONS