Datasheet

LT3825
23
3825fe
C
MILLER
is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 6).
The flat portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops.
The Miller capacitance is computed as:
C
MILLER
=
Q
B
– Q
A
V
DS
The curve is done for a given V
DS
. The Miller capacitance
for different V
DS
voltages are estimated by multiplying the
computed C
MILLER
by the ratio of the application V
DS
to
the curve specified V
DS
.
APPLICATIONS INFORMATION
Q
A
V
GS
a b
3825 F06
Q
B
MILLER EFFECT
GATE CHARGE (Q
G
)
Figure 6. Gate Charge Curve
With C
MILLER
determined, calculate the primary-side power
MOSFET power dissipation:
P
DPRI
= I
RMS(PRI)
2
• R
DS(ON)
1+ δ
( )
+
V
IN(MAX)
•
P
IN(MAX)
DC
MIN
• R
DR
•
C
MILLER
V
GATE(MAX)
– V
TH
• f
OSC
where:
R
DR
is the gate driver resistance (≈10Ω)
V
TH
is the MOSFET gate threshold voltage
f
OSC
is the operating frequency
V
GATE(MAX)
= 7.5V for this part
(1 + δ) is generally given for a MOSFET in the form of a
normalized R
DS(ON)
vs temperature curve. If you don’t have
a curve, use δ = 0.005/°C • ∆T for low voltage MOSFETs.
The secondary-side power MOSFETs typically operate
at substantially lower V
DS
, so you can neglect transition
losses. The dissipation is calculated using:
P
D(SEC)
= I
RMS(SEC)
2
• R
DS(ON)
(1 + δ)
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
T
J
= T
A
+ P
D
• θ
JA
where T
A
is the ambient temperature and θ
JA
is the MOSFET
junction-to-ambient thermal resistance.
Once you have T
J
, iterate your calculations recomputing
δ and power dissipations until convergence.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency
but the high frequency components of these
signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and efficiency.
The LT3825 gate drives will clamp the max gate voltage
to
roughly 7.4V, so you can safely use MOSFETs with max
V
GS
of 10V or larger.
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchro-
nous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary as shown in
the
application on the front page of this data sheet.
However, other schemes are possible. There are gate
drivers and secondary side synchronous controllers avail-
able that provide the buffer function as well as additional
features.