Datasheet

LT3800
17
3800fc
APPLICATIONS INFORMATION
To prevent large input voltage transients and avoid bypass
capacitor heating, a low ESR input capacitor sized for the
maximum RMS current must be used. This maximum
capacitor RMS current follows the relation:
I
RMS
=
I
MAX
V
OUT
V
IN
–V
OUT
()
()
1
2
V
IN
which peaks at a 50% duty cycle, when I
RMS
= I
MAX
/2.
The bulk capacitance is calculated based on an accept-
able maximum input ripple voltage, ∆V
IN
, which follows
the relation:
C
IN(BULK)
= I
OUT(MAX)
•
V
OUT
V
IN
V
IN
•f
O
∆V is typically on the order of 100mV to 200mV. Aluminum
electrolytic capacitors are a good choice for high voltage,
bulk capacitance due to their high capacitance per unit area.
The capacitor voltage rating must be rated greater than
V
IN(MAX)
. The combination of aluminum electrolytic ca-
pacitors and ceramic capacitors is a common approach
to meeting supply input capacitor requirements. Multiple
capacitors are also commonly paralleled to meet size or
height requirements in a design.
Capacitor ripple current ratings are often based on only
2000 hours (three months) lifetime; it is advisable to derate
either the ESR or temperature rating of the capacitor for
increased MTBF of the regulator.
Output Capacitor Selection
The output capacitor in a buck converter generally has
much less ripple current than the input capacitor. Peak-to-
peak ripple current is equal to that in the inductor (∆I
L
),
typically a fraction of the load current. C
OUT
is selected
to reduce output voltage ripple to a desirable value given
an expected output ripple current. Output ripple (∆V
OUT
)
is approximated by:
∆V
OUT
≈ ∆I
L
(ESR + [(8)(f
O
) • C
OUT
]
–1
)
where f
O
= operating frequency.
∆V
OUT
increases with input voltage, so the maximum
operating input voltage should be used for worst-case
calculations. Multiple capacitors are often paralleled to
meet ESR requirements. Typically, once the ESR require-
ment is satisfi ed, the capacitance is adequate for fi ltering
and has the required RMS current rating. An additional
ceramic capacitor in parallel is commonly used to reduce
the effect of parasitic inductance in the output capacitor,
which reduces high frequency switching noise on the
converter output.
Increasing inductance is an option to reduce ESR require-
ments. For extremely low
∆ V
OUT,
an additional LC fi lter
stage can be added to the output of the supply. Application
Note 44 has information on sizing an additional output
LC fi lter.
Layout Considerations
The LT3800 is typically used in DC/DC converter designs
that involve substantial switching transients. The switch
drivers on the IC are designed to drive large capacitances
and, as such, generate signifi cant transient currents them-
selves. Careful consideration must be made regarding
supply bypass capacitor locations to avoid corrupting the
ground reference used by IC.
Typically, high current paths and transients from the input
supply and any local drive supplies must be kept isolated
from SGND, to which sensitive circuits such as the error
amp reference and the current sense circuits are referred.
Effective grounding can be achieved by considering switch
current in the ground plane, and the return current paths of
each respective bypass capacitor. The V
IN
bypass return,
V
CC
bypass return, and the source of the synchronous
FET carry PGND currents. SGND originates at the negative
terminal of the V
OUT
bypass capacitor, and is the small
signal reference for the LT3800.
Don’t be tempted to run small traces to separate ground
paths. A good ground plane is important as always, but
PGND referred bypass elements must be oriented such
that transient currents in these return paths do not corrupt
the SGND reference.
During the dead-time between switch conduction, the
body diode of the synchronous FET conducts inductor