Datasheet

LT3791
24
3791fa
applicaTions inForMaTion
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
n
The PGND ground plane layer should not have any traces
and it should be as close as possible to the layer with
power MOSFETs.
n
Place C
IN
, switch M1, switch M2 and D1 in one compact
area. Place C
OUT
, switch M3, switch M4 and D2 in one
compact area.
n
Use immediate vias to connect the components (includ-
ing the LT3791’s SGND and PGND pins) to the ground
plane. Use several large vias for each power component.
n
Use planes for V
IN
and V
OUT
to maintain good voltage
filtering and to keep power losses low.
n
Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
(V
IN
or PGND).
n
Separate the signal and power grounds. All small-signal
components should return to the SGND pin at one point,
which is then tied to the PGND pin close to the sources
of switch M2 and switch M3.
n
Place switch M2 and switch M3 as close to the control-
ler as possible, keeping the PGND, BG and SW traces
short.
n
Keep the high dV/dT SW1, SW2, BST1, BST2, TG1 and
TG2 nodes away from sensitive small-signal nodes.
n
The path formed by switch M1, switch M2, D1 and the
C
IN
capacitor should have short leads and PC trace
lengths. The path formed by switch M3, switch M4, D2
and the C
OUT
capacitor also should have short leads
and PC trace lengths.
n
The output capacitor (–) terminals should be connected
as close as possible to the (–) terminals of the input
capacitor.
n
Connect the top driver bootstrap capacitor, C1, closely
to the BST1 and SW1 pins. Connect the top driver
bootstrap capacitor, C2, closely to the BST2 and SW2
pins.
n
Connect the input capacitors, C
IN
, and output capacitors,
C
OUT
, closely to the power MOSFETs. These capaci-
tors carry the MOSFET AC current in boost and buck
operation.
n
Route SNSN and SNSP leads together with minimum
PC trace spacing. Avoid sense lines pass through noisy
areas, such as switch nodes. Ensure accurate current
sensing with Kelvin connections at the SENSE resistor.
n
Connect the V
C
pin compensation network close to the
IC, between V
C
and the signal ground pins. The capaci-
tor helps to filter the effects of PCB noise and output
voltage ripple voltage from the compensation loop.
n
Connect the INTV
CC
bypass capacitor, C
VCC
, close to the
IC, between the INTV
CC
and the power ground pins. This
capacitor carries the MOSFET drivers’ current peaks. An
additional 0.1µF ceramic capacitor placed immediately
next to the INTV
CC
and PGND pins can help improve
noise performance substantially.