Datasheet

LT3782
10
3782fg
then R
FREQ1
+ R
FREQ2
should be 80k and V
DELAY
should
be 1V, with V
RSET
= 2.3V then R
FREQ1
= 47.5k and R
FREQ2
= 32.5k (see Figure 3).
Duty Cycle Limit
When DCL pin is shorted to R
SET
pin and switching fre-
quency is less than 250kHz (R
FREQ
> 80k), the maximum
duty cycle of LT3782 will be at least 90%. The maximum
duty cycle can be clamped to 50% by grounding the DCL
pin or to 75% by forcing the V
DCL
voltage to 1.2V with a
resistor divider from R
SET
pin to ground. The typical DCL
pin input current is 0.2μA.
Slope Compensation
The LT3782 is designed for high voltage and/or high
current applications, and very often these applications
generate noise spikes that can be picked up by the cur-
rent sensing amplifi er and cause switching jitter. To avoid
switching jitter, careful layout is absolutely necessary to
minimize the current sensing noise pickup. Sometimes
increasing slope compensation to overcome the noise
can help to reduce jitter. The built-in slope compensa-
tion can be increased by adding a resistor R
SLOPE
from
SLOPE pin to ground. Note that smaller R
SLOPE
increases
slope compensation and the minimum R
SLOPE
allowed is
R
FREQ
/2.
Layout Considerations
To prevent EMI, the power MOSFETs and input bypass
capacitor leads should be kept as short as possible. A
ground plane should be used under the switching circuitry
to prevent interplane coupling and to act as a thermal
spreading path. Note that the bottom pad of the package
is the heat sink, as well as the IC signal ground, and must
be soldered to the ground plane.
In a boost converter, the conversion gain (assuming 100%
effi ciency) is calculated as (ignoring the forward voltage
drop of the boost diode):
V
OUT
V
IN
=
1
1D
where D is the duty ratio of the main switch. D can then
be estimated from the input and output voltages:
D=1
V
IN
V
OUT
;D
MAX
=1
V
IN(MIN)
V
OUT
Figure 3. Increase Delay Time
R
SET
DELAY
LT3782
R
FREQ2
32.5k
R
FREQ1
47.5k
3782 F03
APPLICATIONS INFORMATION