Datasheet

LT3782A
9
3782afb
With a 200ns one-shot timer on chip, the LT3782A provides
fl exibility on the external sync pulse width. The sync pulse
threshold is about 1.2V (Figure 1). This pin can be fl oated
when the sync function is not used.
Current Limit
Current limit is set by the 63mV threshold across SEN1P,
SEN1N for channel one and SEN2P, SEN2N for channel
two. By connecting an external resistor R
S
(see Block
Diagram), the current limit is set for 63mV/R
S
. R
S
should
be placed very close to the power switch with very short
traces. A low pass R
C
fi lter is needed across R
S
to fi lter out
the switching spikes. Good Kelvin sensing is required for
accurate current limit. The input bypass capacitor ground
should be at the same ground point of the current sense
resistor to minimize the ground current path.
Synchronous Rectifi er Switches
For high output voltage applications, the power loss of the
catch diodes are relatively small because of high duty cycle.
If diodes power loss or heat is a concern, the LT3782A
provides PWM signals through SGATE1 and SGATE2 pins
to drive external MOSFET drivers for synchronous recti-
fi er operation. Note that SGATE drives the top switch and
BGATE drives the bottom switch. To avoid cross conduction
between top and bottom switches, the BGATE turn-on is
delayed 100ns (when DELAY pin is tied to R
SET
pin) from
SGATE turn-off (see Figure 2). If a longer delay is needed
to compensate for the propagation delay of external gate
driver, a resistor divider can be used from R
SET
to ground to
program V
DELAY
for the longer delay needed. For example,
for a switching frequency of 250kHz and delay of 150ns,
then R
FREQ1
+ R
FREQ2
should be 80k and V
DELAY
should
be 1V, with V
RSET
= 2.3V then R
FREQ1
= 47.5k and R
FREQ2
= 32.5k (see Figure 3).
Duty Cycle Limit
When DCL pin is shorted to R
SET
pin and switching fre-
quency is less than 250kHz (R
FREQ
> 80k), the maximum
duty cycle of LT3782A will be at least 90%. The maximum
duty cycle can be clamped to 50% by grounding the DCL
pin or to 75% by forcing the V
DCL
voltage to 1.2V with a
resistor divider from R
SET
pin to ground. The typical DCL
pin input current is 0.2µA.
Figure 1. Synchronizing with External Clock Figure 2. Delay Timing
5V TO 20V
VN2222
PULSE WIDTH > 200ns
5k
SYNC
3782A F01
LT3782A
3782A F02
DELAY
BGATE1
SGATE1
SET
APPLICATIONS INFORMATION
Figure 3. Increase Delay Time
R
SET
DELAY
LT3782A
R
FREQ2
32.5k
R
FREQ1
47.5k
3782A F03