Datasheet

LT3763
16
3763fa
For more information www.linear.com/LT3763
INPUT VOLTAGE (V)
0
4
5
7
30
3763 F04a
3
2
10 20
40
1
0
6
MOSFET POWER LOSS (W)
TOTAL
OHMIC
TRANSITIONAL
INPUT VOLTAGE (V)
0
MOSFET POWER LOSS (W)
1.0
1.5
40
3763 F04b
0.5
0
10
20
30
2.5
2.0
TOTAL
OHMIC
TRANSITIONAL
applicaTions inForMaTion
greater than 15V. When operating at higher input voltages,
efficiency can be optimized by selecting a high side MOSFET
with higher R
DS(ON)
and lower Q
G
. The total power loss in
the high side MOSFET can be approximated by:
P
LOSS
= ohmic loss + transition loss
P
LOSS
≈
V
O
V
IN
•I
O
2
R
DS(ON)
• ρ
T
⎛
⎝
⎜
⎞
⎠
⎟
+
V
IN
•I
OUT
5V
⎛
⎝
⎜
⎞
⎠
⎟
•
Q
GD
+ Q
GS
( )
•
2•R
G
+R
PU
+R
PD
( )
⎛
⎝
⎜
⎞
⎠
⎟
• f
SW
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
where r
T
is a dimensionless temperature dependent
factor in the MOSFET’s on-resistance. Using 70°C as the
maximum ambient operating temperature, r
T
is roughly
equal to 1.3. R
PD
and R
PU
are the LT3763 high side gate
driver output impedances: 1.3Ω and 2.2Ω, respectively.
A good approach to MOSFET sizing is to select a high side
MOSFET, then select the low side MOSFET. The trade-off
between R
DS(ON)
, Q
G
, and Q
GS
for the high side MOSFET
is evident in the following example. V
O
is equal to 4V.
These two N-channel MOSFETs are rated for a V
DS
of 40V
and mounted in the same package, but with 8× different
R
DS(ON)
and 4.5× different Q
G
and Q
GD
:
M1: R
DS(ON)
= 2.3mΩ, Q
G
= 45.5nC,
Q
GS
= 13.8nC, Q
GD
= 14.4nC, R
G
= 1Ω
M2: R
DS(ON)
= 18mΩ, Q
G
= 10nC,
Q
GS
= 4.5nC, Q
GD
= 3.1nC, R
G
= 3.5Ω
Power loss for both MOSFETs is shown in Figure 4. Observe
that whereas the R
DS(ON)
of M1 is eight times lower, the
power loss at low input voltages is about equal to that of
M2, and at high voltages, it is four times higher.
Power loss within the low side MOSFET is almost entirely
from the R
DS(ON)
of the FET. Select the low side FET with
the lowest R
DS(ON)
while keeping the total gate charge Q
G
to 30nC or less.
Another power loss related to switching MOSFET selection
is the power lost driving the gates. The total gate charge,
Q
G
, must be charged and discharged each switching cycle,
so the power lost to the charging of the gates is:
P
GATE
= V
IN
• (Q
GLG
+ Q
GHG
) • f
SW
where Q
GLG
is the low side gate charge and Q
GHG
is the
high side gate charge.
The majority of this loss occurs in the internal LDO within
the LT3763:
P
LOSS_LDO
≈ (V
IN
– 5V) • (Q
GLG
+ Q
GHG
) • f
SW
Whenever possible, utilize a switching MOSFET that
minimizes the total gate charge to limit the internal power
dissipation of the LT3763. Some recommended MOSFETs
are listed in Table 3.
Figure 4a. Power Loss Example for M1
Figure 4b. Power Loss Example for M2