Datasheet

LT3751
8
3751fc
pin FuncTions
DONE (Pin 7/ Pin 5): Open Collector Indication Pin. When
the target output voltage (charge mode) is reached or the
FAULT pin goes low, a transistor turns on. This pin needs
a proper pull-up resistor or current source.
CHARGE (Pin 8/Pin 6): Charge Pin. Initiates a new charge
cycle (charge mode) or enables the part (regulation mode)
when driven higher than 1.5V. Bring this pin below 0.3V
to discontinue charging and put the part into shutdown.
Turn-on ramp rates should be between 10ns to 10ms.
CHARGE pin should not be directly ramped with V
CC
or
LT3751 may not properly initialize.
CLAMP (Pin 9/Pin 7): Internal Clamp Voltage Selection
Pin. Tie this pin to V
CC
to activate the internal 5.6V gate
driver clamp. Tie this pin to ground to activate the internal
10.5V gate driver clamp.
FB (Pin 10/Pin 8): Feedback Regulation Pin. Use this pin
to achieve low noise voltage regulation. FB is internally
regulated to 1.22V when a resistive divider is tied from
this pin to the output. FB pin should not float. Tie FB pin
to either a resistor divider or ground.
CSN (Pin 11/Pin 9): Negative Current Sense Pin. Senses
external NMOS source current. Connect to local
R
SENSE
ground connection for proper Kelvin sensing. The current
limit is set by 106mV/R
SENSE
.
CSP (Pin 12/Pin 10): Positive Current Sense Pin. Senses
NMOS source current. Connect the NMOS source terminal
and the current sense resistor to this pin. The current
limit is fixed at 106mV/R
SENSE
in charge mode. The cur-
rent limit can be reduced to a minimum 11mV/R
SENSE
in
regulation mode.
V
CC
(Pin 13/Pin 11): Input Supply Pin. Must be locally by-
passed with high grade (X5R or better) ceramic capacitor.
The minimum operating voltage for V
CC
is 4.75V.
LVGATE (Pin 14/Pin 12): Low Voltage Gate Pin. Connect
the NMOS gate terminal to this pin when operating V
CC
below 8V. The internal gate driver will drive the voltage to
the V
CC
rail. When operating V
CC
higher than 8V, tie this
pin directly to V
CC
.
HVGATE (Pin 15/Pin 13): High Voltage Gate Pin. Connect
NMOS gate terminal to this pin for all V
CC
operating volt-
ages. Internal gate driver will drive the voltage to within
V
CC
– 2V during each switch cycle.
RBG (Pin 16/Pin 14): Bias Generation Pin. Generates a bias
current set by 0.98V/R
BG
. Select R
BG
to achieve desired
resistance for R
DCM
, RV
OUT
, and RV
TRANS
.
NC (Pins 17, 19/Pins 15, 18): No Connection.
RV
OUT
(Pin 18/Pin 16): Output Voltage Sense Pin. Devel-
ops a current proportional to the output capacitor volt-
age. Connect a resistor between this pin and the drain of
NMOS such that:
V
OUT
= 0.98 • N •
RV
OUT
R
BG






− V
DIODE
when RV
OUT
is set equal to RV
TRANS
, otherwise:
V
OUT
= N • 0.98 •
RV
OUT
R
BG
+ V
TRANS
RV
OUT
RV
TRANS
− 1














− V
DIODE
where V
DIODE
= forward voltage drop of diode D1 (refer
to the Block Diagram).
RDCM (Pin 20/Pin 17): Discontinuous Mode Sense Pin.
Senses when the external NMOS drain is equal to 20µA •
R
DCM
+ V
TRANS
and initiates the next switch cycle. Place
a resistor equal to 0.45 times the resistor on the RV
TRANS
pin between this pin and V
DRAIN
.
GND (Pin 21/Pin 21): Ground. Tie directly to local ground
plane.